Simplified NRZ data phase detector with expanded measuring interval
AssigneeRockwell International Corporation
InventorSteven J. Clendening
Life of this patent
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Abstract
A simplified digital NRZ data phase detector is provided with a minimum number of components and with an expanded measuring interval to enable the use of slower speed components. In a phase locked loop application, a first input gate, such as a flip-flop, responds to NRZ data, and a second input gate responds to clock pulses and the output of the first gate. Variable and fixed width correction signals are derived directly from the outputs of the first and second gates, respectively, within a measuring interval initiated by a data transition and terminated by a clock transition. The difference in duration between the directly derived variable and fixed pulses provides phase indication.
Claims17
An NRZ data phase detector comprising:
- phase error means responsive to a data transition for initiating a measuring interval and responsive to a clock transition for terminating said measuring interval, and including means for generating a variable length subinterval between said data transition and a given polarity clock transition and for generating a fixed length subinterval between designated common polarity clock transitions such that said fixed subinterval has a duration of one full clock cycle, the duration difference between said variable subinterval and said fixed subinterval providing phase indication.
An NRZ data phase detector comprising:
- first gate means responsive to a data transition for generating a variable duration pulse;
- and
- second gate means responsive to clock pulses and to the output of said first gate means for generating a fixed duration pulse between designated clock transitions following said data transition, and for terminating said variable duration pulse upon a given clock transition.
An NRZ data phase detector comprising:
- a first flip-flop responsive to a data transition for outputting a variable duration pulse;
- gate means including a second flip-flop responsive to clock pulses and to the output of said first flip-flop for outputting a fixed duration pulse having a duration of one full clock cycle between designated clock transitions following said data transition, said gate means being also for terminating said variable duration pulse upon a given clock transition.
In a phase locked loop having an amplifier with first and second input terminals, an NRZ data phase detector comprising:
- first gate means responsive to a data transition for generating a variable duration pulse;
- second gate means responsive to clock pulses and to the output of said first gate means for generating a fixed duration pulse between designated clock transitions following said data transition, and for terminating said variable duration pulse upon a given clock transition;
- said variable and fixed duration pulses being derived directly from said first and second gate means and delivered directly to, respectively, said first and second input terminals of said amplifier means.
Dependencies are inferred from the claim text.