Programmable logic array with self correction of faults
AssigneeInternational Business Machines Corporation
InventorsVolkmar Gotze, Dieter Schutt
Life of this patent
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Abstract
An apparatus and a method to automatically locate defects and to automatically insert and personalize dummy lines in a PLA having latches controlling the cross points of the AND and OR array. Upon occurrence of an error in the PLA, a check signal is generated which interrupts normal operation of the PLA and which initiates a test procedure. The cross point latches are automatically loaded with test patterns and the output of the PLA is analyzed to locate the defective part, for example, a damaged cross point transistor, short circuited or open line. The dummy lines are repersonalized automatically to replace lines which are defective themselves or which are connected to defective crosspoints.
Claims14
A programming logic array (PLA) having an AND array and an OR array with input lines to the AND array, output lines from the OR array, and product term lines interconnecting the two arrays, the PLA having storage flip-flops at the cross points of the arrays, wherein the improvement comprises,
- means connecting the flip-flops along individual product term lines of the AND array and along individual output lines of the OR array to form shift registers,
- means for sequentially loading data for a test sequence into the shift registers of the PLA,
- whereby the array can be tested to locate faults, and
- dummy lines in the array connectable to replace a line in which a fault is detected.
Dependencies are inferred from the claim text.