Semaphore register including ownership bits

A semaphore register for use in a data processing system to indicate the status of a resource shared by first and second processors, comprising:

• first master latch means for providing an internal ownership signal in a first state in response to a first set signal and in a second state in response to a first reset signal, said first state of said internal ownership signal indicating ownership of said resource by said first processor;
• second master latch means for providing an external ownership signal in a first state in response to a second set signal and in a second state in response to a second reset signal, said first state of said external ownership signal indicating ownership of said resource by said second processor;
• slave latch means coupled to said first and second master latch means, for latching the state of said internal and external ownership signals during a first clock interval, and for providing a semaphore signal in a first state if either of said latched ownership signals is in said first state thereof and in a second state if neither of said latched ownership signals is in said first state thereof;
• first set logic means coupled to said first master and said slave latch means and to said first processor, for providing said first set signal to said first master latch means if, during a second clock interval following said first clock interval, said semaphore signal is in said second state and a first control signal is received from said first processor;
• first reset logic means coupled to said first master latch means, said slave latch means and said first processor, for providing said first reset signal to said first master latch means if, during said second clock interval, said semaphore signal is in said first state and a second control signal is received from said first processor;
• second set logic means coupled to said second master and said slave latch means and to said second processor, for providing said second set signal to said second master latch means if, during a second clock interval following said first clock interval, said semaphore signal is in said second state and a first control signal is received from said second processor;
• second reset logic means coupled to said second master latch means, said slave latch means and said second processor, for providing said second reset signal to said second master latch means if, during said second clock interval, said semaphore signal is in said first state and a second control signal is received from said second processor;
• output means coupled to said slave latch means and to said first and second processors, for providing to said first and second processors a respective output signal corresponding in state to a respective one of said latched ownership signals and a second output signal corresponding in state to said semaphore signal in response to receiving said first control signal respectively therefrom during said second clock interval;
• and
• arbitration logic means coupled to said output means and to said first and second processors, for forcing the output signal provided by said output means to said second processor to said first state to indicate that said resource is unavailable, in response to simultaneously receiving said first control signals from both of said processors.