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US 4,380,756 AGranted
Charge redistribution circuit having reduced area
AssigneeMitel Corporation
InventorAdrian D. Worsman
Life of this patent
Estimating the term…
Abstract
A codec using charge redistribution techniques between two groups of banks of weighted capacitors, which requires substantially reduced chip area as compared to previous codecs of this type. A switching scheme by which the capacitors are switched between themselves to various leads allows the elimination of the previously required largest capacitor of one bank and its replacement by a capacitor of one eighth its value and size (as well as several very small capacitors) in the other bank. The switching scheme also allows the use of only one reference voltage level, whereas in the past two were required.
Claims9
A charge redistribution circuit for translation of an input signal comprising:
- (a) a first plurality of capacitors, one terminal of each capacitor being connected together,
- (b) means for switching said one terminal to a first reference voltage,
- (c) means for selectively switching the other terminal of each capacitor between a first lead and a second lead,
- (d) means for selectively switching the first lead between a source of said input signal, said first reference voltage, and a high impedance,
- (e) a second plurality of capacitors, one terminal of each capacitor being connected together,
- (f) a buffer having its input connected to said one terminal of the second plurality of capacitors, and its output connected to said second lead,
- (g) means for switching the input of the buffer to said first reference voltage,
- (h) means for selectively switching the other terminal of each of the second plurality of capacitors to a third or a fourth lead,
- (i) means for switching the third and fourth leads interchangeably to the first reference voltage and to a second reference voltage having a single polarity with respect to said first reference voltage,
- whereby upon switching of sequences of said other terminal of capacitors of the first plurality of capacitors between the first and second leads, a distribution of charge is effected therebetween, and upon switching of sequences of said other terminal of capacitors of the second plurality of capacitors between the third and fourth leads a distribution of charge is effected therebetween, and
- (j) output means for carrying an output signal from said one terminal of the first plurality of capacitors, resulting from the distribution of charge between the first capacitors and the distribution of charge between the second capacitors.
8 more elements
A method of encoding a sample of an input signal having an unknown amplitude which is lower than a predetermined maximum comprising:
- (a) applying a sample of the input signal to one common terminal of a first plurality of capacitors connected in parallel and connecting the other common terminal to ground, whereby the capacitors are charged to the voltage of the sample of the input signal, the respective capacitance values of the first plurality of capacitors being C, C, 2C, 4C, 8C 16C, 32C and 64C, where C is a constant,
- (b) connecting said one common terminal to ground while switching said other common terminal from ground to the input of a comparator, the other input terminal of the comparator being connected to ground,
- (c) detecting the sign of the output signal of the comparator,
- (d) connecting one common terminal of a second plurality of capacitors to ground,
- (e) connecting the other common terminal of the second plurality of capacitors to one of ground in the event the sign of the output signal of the comparator is positive, or to a supply voltage at least as high as said predetermined maximum in the event the sign of the output signal of the comparator is negative, the respective capacitance values of the second plurality of capacitors being 1/2C, 1/2C, C, C, 2C, 4C, 8C and 16C, where C is said constant,
- (f) switching said other terminal of a 1/2C and a 16C capacitor to the other of the supply voltage or ground,
- (g) switching said one terminal of a C capacitor of the first plurality of capacitors to ground and its other terminal the first common terminal of the second plurality of capacitors via the output of a buffer,
- (h) switching said other terminals of the remaining ones of the first plurality of capacitors to a high impedance, and said one common terminal thereof to ground,
- (i) switching said one terminal of the latter C capacitor to said one common terminal of the first plurality of terminals,
- (j) reswitching said 1/2C capacitor to the first of ground or the voltage supply,
- (k) switching capacitors of the first plurality of capacitors in parallel with said latter C capacitor until the output signal of the comparator changes states,
- (l) switching capacitor having the most significant capacitance from a connection in parallel with said latter C capacitor to a connection in parallel with the remaining first plurality of capacitors,
- (m) switching capacitors of the second plurality of capacitors in parallel with said 16C capacitor of the second plurality of capacitors until the output signal of the comparator changes state,
- whereby the binary value identity of the switched capacitors at the last change of state of the output signal of the comparator designates the digital identification of a PCM word corresponding to the amplitude of the sample of the input signal.
11 more elements
Dependencies are inferred from the claim text.