Monolithically integrated two-dimensional image sensor with a difference forming stage

A monolithically integrated two-dimensional image sensor having a difference-forming stage, said image sensor having a plurality of sensor elements disposed in rows and columns on a doped semiconductor body, with all sensor elements in a column being connected to a common column line selectively connectable to a reference potential, and with all sensor elements in a row being connected to a common row line connected to a means for selectively energizing all sensor elements in a row for collection of radiation incident on said sensor elements, said difference-forming stage comprising:

• a plurality of first oppositely doped regions in said semiconductor body respectively connected to said column lines for generating a charge packet corresponding to respective voltages on said column lines;
• a plurality of storage capacitors formed by respective electrodes disposed above an insulating layer on said semiconductor body, each column line having a storage capacitor associated therewith;
• a first transfer gate having a clock pulse voltage connected thereto disposed on said insulating layer on said semiconductor body between said first oppositely doped regions and said storage capacitors;
• a second oppositely doped region in said semiconductor body connected to a supply voltage;
• a second transfer gate disposed on said insulating layer on said semiconductor body between said storage capacitors and said second oppositely doped region, said second transfer gate connected to a clock pulse voltage;
• a reset means for resetting said electrodes of said storage capacitors to a reference potential after a readout operation;
• and
• a serial output device having a plurality of inputs respectively connected to said electrodes of said storage capacitors for sequentially reading out signals from said electrodes,
• whereby first charge packets are generated in said first oppositely doped regions during a first readout of said sensor elements and said first charge packets are transferred by said first transfer gate into said storage capacitors while the electrodes of these are at said reference potential, the storage capacitors being subsequently disconnected from the reference potential and the first charge packets being transferred then into said second oppositely doped region by said second transfer gate, and whereby second charge packets are generated in said oppositely doped regions by a second readout of said sensor elements and are transferred into said storage capacitors and the voltage of said electrodes of said capacitors corresponding to the difference between said first and second charge packets is subsequently output by said serial output device and said second charge packets are subsequently transferred into said second oppositely doped region by said second transfer gate.