Frequency/phase locked loop circuit using digitally controlled oscillator

A circuit for synchronizing frequency and/or phase of an output signal to a reference frequency signal comprising:

• comparator means coupled to said reference signal and a signal representative of said output signal to determine which of said signals occurs first and generating digital signals increasing or decreasing in steps indicating whether said representative signal should be increased or decreased, the comparator means including compare means and up/down counter means whose input is coupled to said compare means and which provides said digital signals as its output,
• digital-to-analog converter means coupled to said digital signals from the comparator means for generating increasing or decreasing analog controlled voltage steps related to the increasing or decreasing digital signal steps,
• a variable frequency controlled oscillator coupled to said converter means for providing the output signal and for adjusting the frequency of the output signal upward or downward in order to obtain synchronization between said reference frequency signal and said output frequency signal,
• an additional counter whose input is coupled to said output signal and whose output is coupled to said comparator means for dividing down the frequency of said output signal to produce said signal representative of said output signal, and
• means responsive to the occurrence of a rising edge of a reference frequency signal waveform for clearing the additional counter, and resetting the up/down counter means and compare means of the comparator means.

A circuit for synchronizing the frequency and/or phase of an output signal to a reference frequency signal comprising:

• a digitally controlled oscillator for producing said output signal which can be varied dependent upon input digital signals which can be varied and applied to the input of the oscillator,
• up/down counter means coupled to a signal representative of said output signal from said oscillator and to said reference frequency signal for determining which of said signals occurs first and generating one or more of said digital signals increasing or decreasing in steps indicating whether the frequency of said output signal should be increased or decreased,
• an additional counter means whose input is coupled to said output signal and whose output is coupled to said up/down counter means for dividing down the frequency of said output signal and applying the divided down signal as said signal representative of said output signal to the up/down counter means, and
• means responsive to the occurrence of a rising edge of a reference frequency signal waveform for clearing the additional counter and resetting the up/down counter means.

A circuit for synchronizing the frequency and/or phase of an output signal to a reference frequency signal comprising:

• comparator means coupled to said reference frequency signal and a signal representative of said output signal to determine which of said signals occurs first and generating digital signals indicating whether said representative signal should be increased or decreased, the comparator means including up/down counter means,
• a fixed frequency oscillator generating a fixed frequency signal greater than the reference frequency signal,
• a variable modulo counter having as inputs said digital signals and said fixed frequency signal such that discrete changes in said digital signals cause discrete modulus changes in said counter to thereby produce said output signal having a variable frequency which changes in discrete steps, and which is to be synchronized with said reference frequency signal,
• an additional counter means whose input is coupled to said output signal and whose output is coupled to said up/down counter means for dividing down the frequency of said output signal and applying the divided down signal as said signal representative of said output signal to the input of the up/down counter means, and
• means responsive to the occurrence of a rising edge of a reference frequency signal waveform for clearing the additional counter and resetting the up/down counter means.