TTL to CMOS Interface circuit
AssigneeHarris Corporation
InventorsPaul B. Cohen, William R. Young, W. Dale Edwards
Life of this patent
Estimating the term…
Abstract
An interface circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors. The controlled leg of the first current mirror includes a variable current source responsive to the input signal and the controlled leg of the second current mirror includes a variable current sink for improving the response time of the inverter and compensates the inverter for manufacturing tolerances.
Claims10
An interface circuit having a signal input terminal, a reference terminal and a signal output terminal comprising:
- a complementary field effect transistor inverter having an N and P channel device connected between a pair of supply terminals with the input terminal of the circuit being the input of said inverter and the output terminal of said circuit being the output of said inverter;
- a first complementary field effect transistor current mirror means connected between said pair of supply terminals with the reference terminal being the input for the controlling leg and said N channel device being in a first portion of the controlled leg;
- and said signal input being an input to a second portion of the controlled leg;
- and
- a second complementary field effect transistor current mirror means connected between said pair of supply terminals with the reference terminal being the input for the controlling leg and said P channel device being in a first portion of the controlled leg and said input signal being an input to a second portion of the controlled leg.
An interface circuit having an input terminal and output terminal comprising:
- a complementary field effect transistor inverter having an N and P channel device connected between a pair of supply terminals with the input terminal of the circuit being the input of said inverter and the output terminal of the circuit being the output of said inverter;
- a variable current source means in series with the conduction path of said N channel device and in parallel with said P channel device for providing current for said N channel device as a function of the signal on the input terminal;
- and
- a variable current sink means in series with the conduction path of said P channel device and in parallel with said N channel device for providing a sink of current from said P channel device as a function of the signal on the input terminal;
- said variable current source means and said variable current sink means operate to decrease the response time of said inverter.
Dependencies are inferred from the claim text.