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US 4,380,709 AGranted
Switched-supply three-state circuit
AssigneeMotorola, Inc.
InventorKenneth K. Au
Life of this patent
Estimating the term…
Abstract
An MOS switched-supply three-state buffer circuit includes first and second inverter means. When an enabling signal is in the predetermined state, a source voltage is applied to the first and second inverter means to permit the generation of true and complement signal representations of an input signal. When the enabling signal is in other than a predetermined state, the source voltage is blocked and the circuit output is left floating.
Claims9
A switched-supply three-state circuit capable of assuming first, second and third conditions, comprising:
- first means for receiving an enabling signal and a source of supply voltage;
- second means for receiving an input signal;
- third means coupled to said first and second means and having an output for generating true and complement signal representations of said input signal when the source voltage is supplied to said third means, said output being disabled when said source voltage is blocked from said third means;
- and
- fourth means coupled between said first means and said third means for supplying the source voltage to said third means when said enabling signal is in a first predetermined state, comprising:
- first inverter means having a first MOS inverter coupled between ground and said source voltage and having an input coupled to said enabling signal and having an output;
- a first field-effect transistor having a drain coupled to said source voltage, a gate coupled to the output of said first MOS inverter and having a source coupled to said third means for supplying voltage thereto;
- and
- a second field-effect transistor having a source coupled to ground, a gate coupled to said enabling signal and a drain coupled to the source of said first field-effect transistor.
6 more elements
A switched-supply three-state circuit capable of assuming first, second and third conditions, comprising:
- first means for receiving an enabling signal and a source of supply voltage;
- second means for receiving an input signal;
- third means coupled to said first and second means and having an output for generating true and complement signal representations of said input signal when the source voltage is supplied to said third means, said output being disabled when said source voltage is blocked from said third means;
- and
- fourth means coupled between said first means and said third means for supplying the source voltage to said third means when said enabling signal is in a first predetermined state, wherein:
- said third means comprises:
- first inverter means having an input coupled to said input signal and energized by said fourth means for generating the true signal representation and comprising a first MOS inverter having an input coupled to said input signal and having an output and a second MOS inverter having an input coupled to the output of said first MOS inverter for generating said true signal representation;
- and
- second inverter means having an input coupled to said input signal and energized by said fourth means for generating the complement signal representation and comprising a third MOS inverter having an input coupled to said input signal and an output for generating the complement signal representation;
- and
- said fourth means comprises:
- a fourth MOS inverter coupled between ground and said source voltage and having an input coupled to said enabling signal and having an output;
- a third field-effect transistor having a drain coupled to said source voltage, a gate coupled to the output of said fourth inverter and having a source coupled to said second and third inverters for supplying voltage thereto;
- and
- a fourth field-effect transistor having a source coupled to ground, a gate coupled to said enabling signal and a drain coupled to the source of said third field-effect transistor.
12 more elements
Dependencies are inferred from the claim text.