Dynamic zero offset compensating circuit for A/D converter

In an analog device having at least one input and one output and receiving an analog signal with a zero mean value on said input and supplying a signal with a determined relationship with respect to the input signal on its output, an improved compensation circuit for continuously compensating for the zero offset level introduced into the output signal by the device, comprising:

• means for comparing the level of the output signal with the offset zero level and supplying the sign of the output signal with respect to the offset zero level, said sign being positive if the output signal level exceeds that of the offset zero level and negative if the output signal level is less than the offset zero level;
• a storing capacitor having a first terminal M and a second terminal connected to ground;
• charging means for applying a charge current +I to terminal M when the sign of the output signal is negative;
• discharging means for applying a discharge current -I to terminal M when the sign of the output signal is positive;
• and
• means for continuously adding the voltage generated at terminal M in response to the charge and discharge of said storing capacitor to the input signal;
• and wherein said charging and discharging means include two current sources for supplying currents having the magnitude and sign, respectively, of 2I and -I and which are series-connected between two positive and negative voltage supplies, respectively, having their common point connected to terminal M of said capacitor, said two supplies being always switched on, and
• steering means for steering 2I to ground when the sign of the output signal is positive.