Delay stage for a clock generator

A delay stage which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising:

• first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors;
• a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node;
• fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node, and said third node forming the output terminal;
• and
• said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal.

A delay stage which receives an input signal at an input terminal and is powered through first and second power terminals, comprising:

• a first transistor having drain, source and gate terminals, the drain terminal thereof connected to the first power terminal;
• a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said source and gate terminals of said first transistor thereby forming a first node, said gate terminal thereof connected to the input terminal;
• a third transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said second transistor thereby forming a second node, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to the second power terminal;
• a fourth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, said gate terminal thereof connected to said first node, and said source terminal thereof connected to said second node;
• a fifth transistor having drain, source and gate terminals, said drain terminal thereof connected to the first power terminal, and said gate terminal thereof connected to said first node;
• and
• a sixth transistor having drain, source and gate terminals, said drain terminal thereof connected to said source terminal of said fifth transistor, said gate terminal thereof connected to the input terminal, and said source terminal thereof connected to said second node.

A clock generator circuit for producing clocking signals wherein the clock generator circuit receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising:

• Schmitt trigger means connected between the first and second power terminals and to the input terminal for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal;
• buffer means connected between the first power terminal and the Schmitt trigger means for receiving said detection signal;
• a first transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal;
• a second transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said first transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said buffer means;
• third and fourth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node therebetween, said gate terminal of said third transistor being connected to said source terminal of said first transistor and said gate terminal of said fourth transistor being connected to said source terminal of said second transistor;
• capacitor means connected between said source terminal of said first transistor and said first node;
• and
• fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said fifth transistor connected to said gate terminal of said third transistor and said gate terminal of said sixth transistor connected to said gate terminal of said fourth transistor.

A clock generator circuit for producing clocking signals which receives an input signal at an input terminal, produces an output signal at an output terminal and is powered through first and second power terminals, comprising:

• first, second and third transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a first node between said first and second transistors and a second node between said second and third transistors;
• a fourth transistor having drain, source and gate terminals connected between the first power terminal and said second node, said gate terminal thereof connected to said first node;
• fifth and sixth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and said second node, and forming a third node therebetween, said gate terminal of said fifth transistor connected to said first node;
• said gate terminal of said second transistor, said gate terminal of said third transistor and said gate terminal of said sixth transistor being connected to the input terminal;
• a seventh transistor having drain, source and gate terminals, said drain terminal thereof connected to the input terminal;
• an eighth transistor having drain, source and gate terminals, said drain terminal thereof connected to said gate terminal of said seventh transistor, said gate terminal thereof connected to the first power terminal and said source terminal thereof connected to said third node;
• ninth and tenth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming a fourth node therebetween, said gate terminal of said ninth transistor being connected to said source terminal of said seventh transistor and said gate terminal of said tenth transistor being connected to said source terminal of said eighth transistor;
• capacitor means connected between said source terminal of said seventh transistor and said fourth node;
• and
• eleventh and twelfth transistors each having drain, source and gate terminals and being connected in series between the first power terminal and the second power terminal and forming the output terminal therebetween, said gate terminal of said eleventh transistor connected to said gate terminal of said ninth transistor and said gate terminal of said twelfth transistor connected to said gate terminal of said tenth transistor.