Semiconductor memory device
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorsKiyofumi Ochii, Masami Masuda, Takeo Kondo
Life of this patent
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Abstract
A semiconductor memory device includes a plurality of memory cells arranged in a matrix fashion, word lines each connected commonly to the memory cells arranged on the same row, plural pairs of data lines each pair connected commonly to the memory cells on the same column line, and a row decoder connected to the word lines. The semiconductor memory device further includes positive feedback amplifiers connected to the work lines, which respond to voltages on the word lines at a preset or higher level to pull up the potential on the word lines to a higher level.
Claims38
A semiconductor memory device for use with a row decoder supplying row access signals and a column decoder for supplying column access signals, the device comprising:
- at least one memory cell;
- at least one word line connected to said at least one memory cell and receiving the row access signals;
- at least one data line connected to said at least one memory cell to transfer data to and from said at least one memory cell in accordance with said column access signals;
- and
- positive feedback amplifier means coupled with said at least one word line to amplify said received row access signals supplied to said at least one word line and to positively feed back to said at least one word line said amplified row access signals.
A semiconductor memory device for use with a row decoder supplying row access signals and a column decoder for supplying column access signals, the device comprising:
- At least one word line receiving at one end the row access signals and for transmitting the received row access signal therealong, the row access signals being attenuated during transmission from said one end to the other end of said word line;
- a plurality of memory cells connected to said at least one word line;
- a plurality of data lines connected to said memory cells to transfer data to and from said memory cells in accordance with the column access signals;
- and
- positive feedback amplifier means connected proximate to said other end of said word line to amplify said row access signals transmitted to said other end of said word line and to feed back said amplified access signals to said other end of said word line.
A semiconductor memory device for use with a row decoder supplying a row access signal and a column decoder supplying a column access signal, the device comprising:
- at least one word line receiving at one end the row access signal and for transmitting the received row access signal there along to the other end of the word line;
- a plurality of memory cells connected to said word line in a spaced apart manner;
- a plurality of pairs of data lines connected to said memory cells to transfer data to and from said memory cells in accordance with the column access signal;
- and
- positive feedback amplifier means connected to said word line proximate said other end for amplifying the row access signal supplied to said word line and for supplying said amplified row access signal to said word line.
A semiconductor memory device for use with a row decoder supplying a row access signal and a column decoder supplying a column access signal for controlling memory access, the device comprising:
- a plurality of memory cells arranged in a matrix of rows and columns;
- a plurality of word lines, each of the word lines being connected commonly to the memory cells of a different one for the transmission of the row access signal this along from one end to of said rows the other end, the row access being attempted during said transmission;
- a plurality of data lines each connected commonly to the memory cells of a different column in said matrix to transfer data to and from the memory cells in said columns in accordance with said column access signal;
- and
- positive feedback amplifying means coupled to one end of each of said word lines for amplifying the access signal supplied to said word lines and for supplying said amplified row access signal to said word line whereby the attenuation of said signal level of said row access signals is compensated for by said positive feedback amplifying means.
A semiconductor memory device for use with a row decoder supplying row access signals and a column decoder supplying column access signals, the device comprising:
- at least one word line for receiving the row access signal at one end and for transmitting the received row access signal there along, the level of the row access signal being attenuated during transmission from said one end of said word line;
- a plurality of memory cells connected to said word lines;
- plural pairs of data lines connected to said memory cells for transferring data to and from said memory cells in accordance with the column access signals;
- and
- positive feedback amplifier means connected to said word line proximate the other end of said word line for amplifying the row access signals supplied to said one end of said word line and for supplying said amplified row access signal to said word line proximate said other end to compensate for the attenuation of said row access signal transmitted along said word line.
Dependencies are inferred from the claim text.