Modular system controller for a transition machine

A computing system for solving a plurality of disjoint computational problems, each said disjoint computation problem solved by execution of a plurality of application programs and a control program, said system comprising:

• (a) a plurality of data processors connected for accessing application program memory storage means storing said application programs and data memory storage means storing data elements, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors and at least one of said plurality of data processors including means for generating at least one variable status indication determined upon execution of at least one of said plurality of application programs;
• (b) a plurality of system controller modular units, each unit operable for execution of one of said control programs for controlling execution of application programs corresponding to a different one of said disjoint computational problems, each unit including:
• (1) a status register for storing status indications S.sub.j of a plurality of data conditions appropriate for said one of said disjoint computational problems;
• (2) a relevance matrix store for storing indications R.sub.ij of the relevance of each data condition j to each application program i of said corresponding plurality of application programs;
• (3) means connected to said status register and responsive to said at least one variable status indication for updating said status indications of said status register said at least one variable status indication indicating satisfaction of a data condition, said data condition being a logical relationship involving at least one of said data elements, said at least one data element having a value determined by said at least one data processor upon execution of said at least one application program, said updating means including means for modifying a plurality of said status indications in response to execution of one of said applications;
• (4) means for storing a plurality of application program designation addresses corresponding to each application program;
• (5) means responsive to said status indications of said status register, said corresponding relevance indications of said relevance matrix store and said application program designation addresses of said application program designation storing means for determining the eligibility of each application program for execution by said plurality of data processors and for generating designation addresses from said application program designation address storage means for application programs determined to be eligible, wherein eligible programs are executed concurrently in said plurality of data processors;
• and
• (6) synchronization and control logic means for synchronizing and controlling operation of said system controller modular unit;
• whereby said system controller modular units form a hardware executive apparatus for said computing system;
• and
• (c) interface means connected between said plurality of data processors and said plurality of system controller modular units.

A modular computing system comprising:

• (a) a plurality of data processors connected for accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means;
• (b) a plurality of Z modular units, each modular unit including:
• (1) a status register for storing M binary status indications of M data conditions appropriate for partially determining the eligibility of said application programs stored in said application program memory storage means, Z and M being integers, at least one status register of at least one modular unit storing said variable status indication received from at least one of said data processors;
• (2) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of said application programs;
• and
• (3) means connected to said status register for updating said M binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication;
• (c) means for storing a plurality of application program designation addresses corresponding to said application programs;
• (d) means connected to said relevance matrix stores and said status registers for determining the eligibility of said application programs for execution by said plurality of data processors, said eligibility determining means responsive to said ZM binary status indications of said Z status registers and said corresponding ZM binary relevance indications of said Z relevance matrix stores;
• (e) logic circuit means for synchronizing and controlling said modular units, for scheduling execution of said application programs, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation address for application programs determined to be eligible;
• and
• (f) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and
• whereby Z modular units may be utilized in said computing system for increasing the number of data conditions for a computational problem to be solved by said computing system.

A modular computing system comprising:

• (a) a plurality of data processors accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means;
• (b) a system controller comprising:
• (1) a status register for storing M binary status indications of a plurality of M data conditions appropriate for determining the eligibility of up to ZN application programs stored in said application program memory storage means, Z, M and N being integers and N being less than the number of application programs stored in said application program memory storage means and utilized for solving a computational problem by said computing system,
• (2) a plurality of Z modular units, each modular unit including:
• (i) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of as many as N application programs, said relevance indications being different from one modular unit to another and corresponding to different groups of application programs, each group having as many as N application programs;
• (ii) means connected to said status register for updating said binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication for updating said binary status indications in response thereto;
• and
• (iii) means for storing up to ZN application program designation addresses corresponding to said application programs;
• and
• (3) means connected to said relevance matrix stores and said status register for determining the eligibility of said up to ZN application programs for execution by said plurality of data processors, said eligibility determining means responsive to said M binary status indications of said status register and said M corresponding binary relevance indications of said relevance matrix store;
• (4) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible;
• and
• (c) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and
• whereby any number of Z modular units may be utilized in said computing system for increasing the number of application programs utilized for solving a computational problem by said computing system.