Low power differential amplifier
AssigneeMostek Corporation
InventorIan A. Young
Life of this patent
Estimating the term…
Abstract
A differential amplifier (24, 26, 10 and 12) having a feedback network (30, 34, 32, 36 and 38) for increasing common output without loss of gain. Also disclosed is a constant current source (60), and a level shifting network (48, 50, 52 and 54) for shifting the D.C. level of the output signal to a D.C. voltage substantially near that of second current source (44). An output stage (84, 86, 90, 92 and 94) provides low output impedance, low D.C. bias power consumption and high current drive capability.
Claims31
A differential amplifier for connection to a first voltage source (28) to amplify a difference signal, said differential amplifier having two input terminals (14 and 20) and first and second output terminals (16 and 22) and having a feedback node (18), and having a feedback means comprised of:
- a first MOSFET (30) having a source, drain and gate, said gate coupled to said first output terminal (16), said drain for connection to a first voltage source (28) and said source (46) for connection to a first current source means for supplying a substantially constant current, for providing a first feedback signal at said source (46) proportional to the signal at said first output terminal (16);
- a second MOSFET (34) having a source, drain and gate, said gate coupled to said source (46) of said first MOSFET and said drain coupled to said first output terminal (16) and said source coupled to a second current source means for supplying a substantially constant current, for providing a negative second feedback signal to said first output terminal (16) tending to keep the voltage on said terminal substantially constant;
- a third MOSFET (38) having a gate, drain and source, said drain coupled to said feedback node (18), said gate coupled to said source (42) of said second MOSFET and said source for coupling to a second voltage source (44) for receiving said first feedback signal and for converting it to a third negative feedback signal at said feedback node (18) causing said differential amplifier to reject substantially all common mode input signals and causing substantially all of the amplified difference signals to appear at said second output terminal (22).
A differential amplifier having a pair of input terminals (14 and 20) and first (16) and second (22) output terminals for amplifying a difference signal present between said input terminals which comprises:
- first and second depletion mode MOSFETs (24 and 26) each having a drain, a source, and a gate, said drains for coupling to a first voltage source (28) and said gate of said first MOSFET coupled to its source (16) and said gate of said second MOSFET coupled to its source (22);
- a third MOSFET (10) having a drain, source, and gate, said drain coupled to said first output terminal (16);
- a fourth MOSFET having a drain, source and gate, said drain coupled to said output terminal (22), said gate coupled to the other of said input terminals (20) and said source coupled to said source (18) of said third MOSFET;
- a fifth MOSFET having a drain, source and gate, said gate coupled to said first output terminal (16) and said drain for coupling to said first voltage source (28);
- a sixth MOSFET having drain, source and gate, said gate coupled to said source (46) of said fifth MOSFET, and said drain coupled to said first output terminal (16);
- a second current source means coupled to said source (42) of said sixth MOSFET and for coupling to said second voltage source (44) for causing a substantially constant current to flow through said sixth MOSFET;
- a seventh MOSFET (38) having a gate, drain and source, said gate coupled to said source (42) of said sixth MOSFET, said drain coupled to said source (18) of said third MOSFET and said source for coupling to said second voltage source (44).
A differential amplifier having a pair of input terminals (14 and 20) and first and second output terminals (16 and 22) for amplifying a difference signal present between said input terminals which comprises:
- first and second depletion mode MOSFET each having a drain, a source, and a gate, said drains for coupling to a first voltage source (28) and said gate of said first MOSFET coupled to its source (16) and said gates for coupling to a third voltage source having a predetermined characteristic;
- a third natural MOSFET having an unimplanted channel and having a drain, source, and gate, said drain coupled to said first output terminal (16), said gate coupled one of said input terminals;
- a fourth natural MOSFET having an unimplanted channel and having a drain, source and gate, said drain coupled to said second output terminal (22), said gate coupled to the other of said input terminals (20) and said source coupled to said source (18) of said third MOSFET (10);
- a fifth MOSFET (30) having a drain, source and gate said gate coupled to said first output terminal (16) and said drain for coupling to said first voltage source (28);
- a first current means source coupled to said source of said fifth MOSFET and for coupling to a second voltage source (44) for causing a substantially constant current to flow;
- a sixth MOSFET (34) having drain, source and gate, said gate coupled to said source of said fifth MOSFET, and said drain coupled to said first output terminal (16);
- a second current source means coupled to said source of said sixth MOSFET (34) and for coupling to said second voltage source (44) for causing a substantially constant current to flow through said sixth MOSFET;
- a seventh MOSFET (38) having a gate, drain and source, said gate coupled to said source (42) of said sixth MOSFET, said drain coupled to said source (18) of said third MOSFET and said source for coupling to said second voltage source (44);
- a means coupled between said second output terminal (22) and said second voltage source (44) for shifting the D.C. level of the amplified difference signal appearing on said second output terminal (22) to a D.C. level substantially near said second voltage source (44) voltage level and having a third output terminal (58).
A differential amplifier for connection to a first voltage source to amplify a difference signal having two input terminals (14 and 20) and first (16) and second (22) output terminals and having a feedback node (18) and having a feedback means including:
- a first MOSFET (30) having a source, drain and gate, said gate coupled to said first output terminal (16), said drain for connection to a first voltage source (28);
- a first current source means coupled to said source (46) of first MOSFET (30) for supplying a substantially constant current;
- a second MOSFET (34) having a source, drain and gate, said gate coupled to said source (46) of said first MOSFET (30) and said drain coupled to said first output terminal (16);
- a second current source means coupled to the source (42) of second MOSFET (34) for supplying a substantially constant current;
- a third MOSFET (38) having a gate, drain and source, said drain coupled to said feedback node (18), said gate coupled to said source (42) of said second MOSFET (34), said source for coupling to a second voltage source (44);
- a means coupled between said second output terminal (22) and a second voltage source (44) for shifting the D.C. level of the amplified difference signal appearing on said second output terminal (22) to a D.C. level substantially near said second voltage source (44) voltage level and having a third output terminal (58).
An output stage for an operational amplifier comprising:
- a first MOSFET (84) having a drain, gate and source, said drain for coupling to a first voltage source (28), said gate coupled to the output terminal of said operational amplifier, said source coupled to the output terminal (88) of said output stage;
- a second MOSFET (90) having a drain source and gate, said drain for coupling to a first voltage source (28), said gate coupled to an inverted output of said operational amplifier;
- a third MOSFET (92) having a drain, source and gate, said drain coupled to said source (96) of said second MOSFET, said source for coupling to a second voltage source (44), and said gate coupled to said output terminal of said operational amplifier;
- a fourth MOSFET (86) having a drain source and gate, said gate coupled to said source (96) of said second MOSFET, said drain coupled to the output terminal (88) of said output stage, and said source for coupling to said second voltage source (44);
- and
- a fifth MOSFET (94) having its drain for coupling to said first voltage source (28) and its gate coupled to said output terminal (88) of said output stage and having its source coupled to said gate (96) of said fourth MOSFET (86).
A differential amplifier for amplifying a difference signal comprising:
- two input terminals (14 and 20);
- two output terminals (16 and 22);
- a feedback node (18);
- a feedback means coupled between one of said terminals (16) and said feedback node (18) for causing substantially all of the amplified difference signal to appear at the other said output terminal (22) and for increasing common mode rejection;
- a first MOSFET (48) having a source, drain and gate, said drain for coupling to said first voltage source (28) and said gate coupled to said second output terminal (22);
- a second MOSFET (50) having a source, drain and gate, said drain coupled to said second output terminal (22) and said gate coupled to said source of said first MOSFET;
- a first current source means coupled to said source (56) of said first MOSFET for causing a substantially constant drain current to flow in said first MOSFET;
- a second current source means coupled to said source (58) of said second MOSFET for causing a substantially constant drain current to flow through said second MOSFET.
Dependencies are inferred from the claim text.