Dual clocking time delay generation circuit
AssigneeBurroughs Corporation
InventorRobert D. Catiller
Life of this patent
Estimating the term…
Abstract
A control circuit for generating first and second clocking pulses as outputs wherein there is a controlled time delay between the first and the second clocking pulses. The delay time, d.sub.i, between the first and second clocking pulses can be controlled as to the duration of the delay and also can be placed on an automatic sequence basis wherein the time delay d.sub.i period will automatically readjust to a series of smaller time delay periods.
Claims11
A circuit for generating two separate clocking signals having a delay period, d.sub.i, therebetween, said dual clocking delay circuit comprising:
- (a) first means to generate a ramp voltage;
- (b) second means to generate an analog voltage proportional to a time period;
- (c) third means to set an initial voltage representing a time (T.sub.0) which will initiate a first output clock signal when said ramp voltage is equal to said initial voltage;
- (d) fourth means to provide a first output clock signal at said time (T.sub.0);
- (e) fifth means to initiate a second output clock signal at a time (T.sub.1) upon sensing voltage equality between said ramp voltage and said time period analog voltage;
- (f) reference clock means to energize said first and second means.
A dual clocking circuit providing a variable delay period between first and second clock signals, said dual clocking delay circuit comprising:
- (a) a master reference clock for clocking a digital down counter and a capacitor bank;
- (b) a digital down counter clocked by said reference clock and providing variable time signals to a digital-analog converter;
- (c) first comparator means including:
- (c1) a reference voltage input;
- (c2) a ramp voltage input;
- (c3) a first clocking signal output;
- (d) second comparator means including:
- (d1) a time period-referenced analog voltage input;
- (d2) a ramp voltage input;
- (d3) a second clocking signal output;
- (e) digital-analog conversion means for converting a digital time period signal into an analog signal for input to said second comparator means;
- (f) ramp voltage generation means including:
- (f1) an adjustable constant current source for energizing a ramp-voltage line;
- (f2) a capacitor bank connected to said ramp-voltage line and energized by said reference clock;
- (f3) a ramp voltage output line connected to said adjustable constant current source and said capacitor bank and providing a ramp voltage output signal to said first and second analog comparators;
- and wherein said second clocking signal is activated in a time delayed period after said first clocking signal.
Dependencies are inferred from the claim text.