Dual-slope integrator

A dual-slope integrator comprising:

• an integrating network including an integrating capacitor;
• first and second switches respectively triggerable to apply a measurement voltage and a reference voltage to an input of said integrating network;
• a control circuit connected to said switches for triggering same;
• a clock pulse generator connected to said control circuit for triggering said switches in the cadence of the clock pulses of said generator;
• a first counter having a count capacity N.sub.1 and a second counter having a count capacity N.sub.2 connected to said control circuit for counting clock pulses during integration of said voltages, said clock pulse generator being connected to said counters by said control circuit upon application of a signal thereto;
• an amplifier having an amplification factor N*.sub.2 .perspectiveto.N.sub.2 connected to said integrator capacitor and having an output;
• a third switch connected between said output of said amplifier and a terminal of a holding capacitor, said third switch being triggerable by said control circuit;
• a fourth switch connected between said terminal of said holding capacitor and said input of said integrating network and triggerable by said control circuit;
• and
• a comparator connected in parallel with said amplifier to said integrating network and controllingly coupled with said control circuit to apply said signal thereto and so that said holding capacitor is connected to said input of said integrating network to apply a residual voltage of the integrating network amplified by the factor N*.sub.2 to the integrating network after the first zero passage of the reference voltage and simultaneously form a combined count in said counters of a value Z.sub.1 .times.N.sub.2 -Z.sub.2 under the control of the reference voltage where Z.sub.1 and Z.sub.2 are the counts in the first and second counters respectively, said control circuit being provided with a delay for triggering said third and fourth switches following the zero passages of the comparator output beyond the subsequent flank of a clock pulse by a fixed delay greater than the width of disturbance pulses, said delay corresponding to a fixed pulse count increasing the backward count in the combined counters, said reference voltage being the same for each control of the formation of said combined count.