US 4,379,241 A · Edge defined output buffer circuit

Abstract

A three-state MOS circuit for buffering an input signal includes an edge definition circuit which is controlled by first and second independent clock signals. The edge definition circuit includes a first transistor for producing a low-to-high voltage transition when the input signal goes from a high to a low, and a second transistor for producing a high-to-low voltage transition in response to the input signal going from a low to a high. The generation of these high-to-low and low-to-high transitions are controlled by first and second independent clock signals. The output of the edge definition circuit is applied to a driver circuit which generates output control signals. The output control signals are applied to first and second output field effect transistors so as to generate a signal representative of the input signal. The circuit is also provided with means for receiving a three-state control signal, which means is controlled by a third clock signal for disabling the driver portion of the buffer circuit so as to render the circuit output floating.

Claims11

Dependent claims

An edge definition circuit for synchronizing an input signal with first and second clock signals, comprising:

first means coupled to said input signal and to said first clock signal for producing a first voltage transition on an output node in response to a voltage transition of said input signal, said first voltage transition occuring at a time determined by said first clock signal;
and
second means coupled to said first means and said second clock signal for producing a second voltage transition on said output node in response to another transition of said input signal, said second voltage transition occurring at a time determined by said second clock signal.

A circuit for buffering an input signal in accordance with occurrences of first and second clock signals, comprising:

first means coupled to said input signal and to said first clock signal for producing a first voltage transition in response to a voltage transition of said input signal, said first voltage transition occurring at a time determined by said first clock signal;
second means coupled to said first means and said second clock signal for producing a second voltage transition in response to another transition of said input signal, said second voltage transition occurring at a time determined by said second clock signal;
driver circuit means coupled to said first and second means and responsive to said first and second voltage transitions for generating output control signals;
and
output means coupled to said driver circuit means for receiving said output control signals and generating therefrom an output representative of said input signal.

2 more elements

Dependencies are inferred from the claim text.

Edge defined output buffer circuit

Life of this patent

Edge defined output buffer circuit

Life of this patent

Abstract

Claims11