High speed shift register
AssigneeNCR Corporation
InventorsAlan B. Hayter, Bernard L. Reagan, Jr.
Life of this patent
Estimating the term…
Abstract
A high speed shift register device includes first and second shift registers. Odd numbered bits of a word are stored in the first shift register and even numbered bits of the word are stored in the second shift register. The first shift register is clocked by a clock signal, and the second shift register is clocked by the complement of the clock signal. The outputs of the first and second shift registers are alternately shifted by means of a multiplexer to an output conductor. A control input of the multiplexer is connected to the clock input. Data is shifted out of the multiplexer at a rate which is twice the normal shifting rate of each of the first and second shift registers.
Claims10
A high speed shift register circuit comprising in combination:
- first shift register means having a first output conductor, said first shift register means being responsive to a leading edge of a first clock signal for serially shifting data in said first shift register means onto said first output conductor;
- second shift register means having a second output conductor, said second shift register means being responsive to a leading edge of a second clock signal for serially shifting data in said second shift register means onto said second output conductor;
- means for producing said first and second clock signals, said second clock signal being the logical complement of the first clock signal, the delay between a leading edge of said first clock signal and a corresponding trailing edge of said second clock signal being less than a predetermined value;
- first means for logically combining a signal on said first output conductor with said second clock signal to produce a first signal;
- second means for logically combining a signal on said second output conductor with said first clock signal to produce a second signal;
- and
- third means having a third output conductor, said third means being responsive to the signals produced by said first and second means for producing a third signal wherein data contained in said first and second shift register means is interleaved and serially shifted onto said third conductor at a rate which is equal to a multiple of the frequency of said first clock signal.
A method for converting a data word in parallel format to serial format and for serially shifting the data word at a high rate, said method comprising the steps of:
- (a) loading the odd numbered bits of said data word into a first shift register and loading the even number bits of said data word into a second shift register;
- (b) applying a first clock signal to a clock input of said first shift register and applying a second clock signal to a clock input of said second shift register, said second clock signal being the logical complement of said first clock signal;
- (c) shifting successive ones of said odd numbered bits of said data word out of said first shift register in response to leading edges of successive pulses of said first clock signal, and shifting successive ones of said even numbered bits of said data word out of said second shift register in response to the leading edges of successive pulses of said second clock signals;
- (d) logically combining the odd numbered bits shifted out of said first shift register with said second clock signal;
- (e) logically combining the even numbered bits shifted out of said second shift register with said first clock signal;
- and
- (f) logically combining the logic signals produced as a result of steps (d) and (e) to produce said data word in said serial format.
Dependencies are inferred from the claim text.