Circuit for detecting phase relationship between two signals

Abstract

A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of a selected one of the input signals and comprising first and second Exclusive OR gates each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. Further connections supply the first and second input signals to the first input terminal of the first and second Exclusive OR gates, respectively. Also provided is a decoder responsive to the output signals of the first and second Exclusive OR gates to determine the phase relationship of the first and second signals at each level transition of the selected input signal and for generating and supplying to the input terminals of the first and second Exclusive OR gates, after each determination of phase relationship, an acknowledgment signal which prepares the circuit for the reception of the next transition of the selected input signal.

Dependencies are inferred from the claim text.