Synchronous multivalued latch
AssigneeThe Regents of the University of California
InventorKarl W. Current
Life of this patent
Estimating the term…
Abstract
A synchronous multivalued latch for storing logical current values of input current having any one of a plurality of multivalues, including a quantizer for receiving current, for generating a logical current being a quantization of the received current, and for regenerating the received current from the logical current as an output, an input line for directing the input current to the quantizer as the received current, a feedback line for directing the regenerated current back to the quantizer as the received current, and a clock controlled switching device for coupling the input line to the quantizer while decoupling the feedback line from the quantizer during a setup mode and for decoupling the input line from the quantizer while coupling the feedback line to the quantizer during a hold mode.
Claims10
A synchronous multivalued latch for storing logical current values of a first input current having any one of a plurality of multivalues, comprising:
- (a) quantizer means, having an input and an output, for generating a logical current being a quantization of current being received at said input and for regenerating the received current in response to the logical current to produce a second regenerated current at said output;
- (b) first means for directing the first input current to said input of said quantizer means;
- (c) second feedback means for directing the second regenerated current from said output to said input of said quantizer means;
- and
- (d) clock controlled switch means for decoupling said first directing means or said second feedback directing means from said input of said quantizer means to direct the second regenerated current or the first input current, respectively, to said input of said quantizer means as the received current.
A synchronous quadra-stable latch for storing logical current values of first input current having any one of four values, comprising:
- (a) a quantizer having an input for receiving current, a first output, a second output, means for converting the received current at said input to a voltage proportional to the received current, first means, having a first voltage threshold, for comparing the voltage to the first voltage threshold to generate first uncomplemented and complemented logical currents, second means, having a second voltage threshold, for comparing the voltage to the second voltage threshold to generate second uncomplemented and complemented logical currents, third means, having a third voltage threshold, for comparing the voltage to the third voltage threshold to generate third complemented and uncomplemented logical currents, first means for summing the first, second and third uncomplemented logical currents to produce a summed uncomplemented logical current, second means for summing the first, second and third complemented logical currents to produce a summed complemented logical current, and means for converting the summed complemented logical current to a second regenerated current corresponding to the received current at said input and for producing the second regenerated current at said first output and said second output;
- (b) first means for directing the first input current to said input;
- (c) second feedback means for directing the second regenerated current at said first output to said input;
- and
- (d) clock controlled switch means for coupling said first directing means to said input while decoupling said second feedback directing means from said input and for coupling said second feedback directing means to said input while decoupling said first detecting means from said input.
Dependencies are inferred from the claim text.