Time base conversion apparatus

A circuit for expanding the time base of a digital input signal comprising:

• memory means having a recurring memory cycle formed of a read phase and a write phase and into which said digital input signals are written at a write clocking rate during said write phase and from which the written-in signals are thereafter read out at a lower read clocking rate during said read phase;
• latch means in advance of said memory means for storing said input digital signal and applying the same in parallel form to said memory means;
• read clock means for generating read clock pulses at said read clocking rate;
• write clock means for generating write clock pulses at said write clocking rate, said read and write clock pulses being asynchronous with each other;
• said digital input signal being written into said memory means and read out therefrom as a block unit, with a read block signal being generated to indicate that one such block unit is in condition to be read out therefrom;
• said memory cycle being synchronized with said read clock pulses upon the occurrence of said read block signal so that, if said read block signal occurs during the read phase of said memory cycle, said read phase is repeated and an occurrence of said write phase is omitted;
• and
• said memory means including a number n of memory banks, said latch means includes a number M of latching stages for each said memory bank coupled in sequence in advance of the respective memory bank, each latching stage having a number N of channels, each said channel processing a predetermined subgroup of a group of words;
• with n, M and N being positive integers selected to be sufficient to prevent said input digital signal from overwriting in said latch means.