US 4,378,591 AGranted

Memory management unit for developing multiple physical addresses in parallel for use in a cache memory

AssigneeHoneywell Information Systems Inc.

InventorRichard A. Lemay

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Abstract

A cache memory for use in a data processing system wherein data words are identified by either an odd or an even address number and wherein system elements request the transfer of data words with the cache memory by supplying either an odd or an even memory request address number with a memory request, the cache memory including a first pllurality of addressable memory locations for storing data words associated with odd address numbers and a second plurality of memory locations for storing data words associated with even address numbers, and an adder for incrementing a memory request address number by one to generate the address number of the next successively stored data word to permit a set of memory address drivers to control the addressing and transferring of a data word stored in the first memory module and associated with an odd address number simultaneously with the addressing and transferring of a data word stored in the second memory module and addressed by an even address number.

Claims10

Dependent claims

In a data processing system wherein data words are associated with either an odd address number or an even address number and wherein system elements request transfers of data words with a cache memory by supplying to the cache memory either an odd or an even memory request address number, the cache memory comprising:

memory means for storing a subset of said data words stored in said system memory, said memory means including an odd memory module having a first plurality of addressable memory locations, each of said first memory locations being associated with a different one of a plurality of odd address numbers, and an even memory module including a second plurality of memory locations, each of said second memory locations being associated with a different one of a plurality of even address numbers, said memory means for selectively outputting data words stored in said odd and even memory modules when addressed by said associated odd and even address numbers, respectively;
means for receiving each of said supplied odd and even memory request address numbers;
means for simultaneously incrementing by one a said received memory request address number to generate an incremented address number, said memory request address number and said incremented address number comprising a pair of address numbers including an odd address number and an even address number;
means for addressing said odd memory module and said even memory module in accordance with said pair of address numbers to output a data word associated with a said even address number and a data word associated with a said odd address number;
and
means for receiving said data words outputted in response to addressing said odd and even memory modules by said pair of address numbers.

3 more elements

A cache memory wherein data words are stored in a plurality of storage locations, each of the storage locations being associated with a unique odd or even address number and wherein system elements coupled to the cache memory request transfers of data words with the cache memory by supplying to the cache memory either an odd or an even memory request address number corresponding to one of the storage locations in the cache memory, the cache memory comprising:

memory means for storing a sequence of said data words, said memory means including an odd memory module for storing said data words in said sequence associated with said odd address numbers and an even memory module for storing said data words in said sequence associated with said even address numbers, said odd and even memory modules including said storage locations associated with said odd and even address numbers, respectively;
means for receiving said memory request address numbers supplied by said system elements;
means for generating the address number associated with the next successive data word in said sequence with respect to said data word associated with a said received memory request address number;
means for simultaneously addressing said storage locations in said odd and even memory modules associated with a said received memory request address number and said generated address number to output said addressed data words;
and
means for receiving said data words outputted by said memory means in response to said addressing by said addressing means.

3 more elements

Dependencies are inferred from the claim text.