Undirectional looped bus microcomputer architecture

A unidirectional looped bus apparatus for communicating data and address signals with respect to a computing module, comprising:

• input bus means in unidirectional attachment with said module for loading signals into said module;
• output bus means in unidirectional attachment with said module for receiving signals from said module;
• first storage means in bidirectional attachment to said input bus means;
• second storage means;
• third storage means for storing executable instruction signals;
• and
• gating and control means connected to each said storage means and controlling said computing module for gating address, instruction, and data signals with respect to the bus and storage means during respective portions of overlapped present and subsequent instruction execution cycles, said gating and control means
• (a) gating during a first cycle portion onto said output bus means from said module address signals for addressing subsequent instruction signals in said third storage means for loading onto said input bus means and then
• (b) gating, during a second instruction cycle portion with respect to a present instruction, incremented or decremented address signals from said module to said output bus means for storing in said second storage means and for addressing a location in said first storage means for selectively loading to or storing data signals with respect to said input bus means.

Looped bus control means for transferring data and address signals over a looped bus with respect to a computing module and a plurality of connected input/output devices and storage devices, comprising:

• said storage devices including first storage means for storing executable instruction signals and second storage means for storing data signals;
• said looped bus including output bus means in unidirectional attachment to said computing module for selectively communicating data and address signals from said computing module;
• register means for storing in a first register location address signals communicated on said output bus means and in a second register location data signals from said output bus means;
• said looped bus further including input bus means in unidirectional attachment to said computing module and interconnecting said register means and said computing module for communicating data and address signals to said computing module from said register means and from said first storage means and interconnecting said second storage means and said register means for communicating data signals received by said register means to said second storage means;
• and
• timing and control means connected to each said storage means and computing module for controlling the loading of address and data signals onto said buses to overlap and pipeline execution of present and subsequent instructions by said computing module, said timing and control means
• (1) controlling the loading from said computing module onto said output bus means of first address signals for accessing subsequent instruction signals from said first storage means to said input bus means while said computing module is executing said present instruction;
• and
• (2) controlling the loading onto said output bus means from said computing module of data resulting from execution of said present instruction while controlling the loading of said subsequent instruction signals from said input bus means into said computing module.

A method for transferring data signals from a computing module having a unidirectional looped bus including a bus out and a bus in, both in unidirectional attachment with said computing module, selectively through a storage register to an addressable location in a main storage device or directly to an I/O device, and for transferring in overlapped mode instruction signals over said bus in to said module from an instruction store addressed by said bus out, comprising the steps of

• loading said data signals onto said bus out selectively for communication to said I/O device and to a local storage register;
• and then,
• loading from said computing module onto said bus out address signals for said instruction store and then gating onto said bus in instruction signals from the instruction store for a subsequent instruction to be executed by said module;
• and then
• loading onto said bus out from said computing module the address in said main storage device into which said data is to be stored from said local storage register;
• while
• loading said data signals from said local storage register onto said bus in for communication to the location in said main storage device addressed by said bus out.

In a computing system, apparatus for communicating data signals with respect to a main storage device and at least one input/output device, comprising:

• central processing means;
• first bus out means for communicating signals from said central processing means for addressing said input/output device;
• control program storage means;
• second unidirectional bus out means selectively operable for communicating signals from said central processing means for addressing said main storage device and said control program storage means, and for transferring data signals to said input/output device;
• bus in means unidirectional with respect to said central processing means selectively operable for transferring data signals from said input/output device to said main storage device and for transferring data signals from said main storage device to said central processing means for loading onto said second bus out means;
• storage register means addressed by said central processing means on said first bus out means for storing first main storage device addresses received from said central processing means on said second unidirectional bus out means for selective loading onto said bus in means for communication to said central processing means;
• and control means selectively for controlling the loading from said processing means onto said second bus out means of address signals for accessing to said bus in means from said control program storage means a control program instruction for subsequent execution, and thereafter of address signals for addressing a location in said main storage device selectively for writing data signals from and loading data signals to said bus in means;
• whereby said processing means overlaps execution of consecutive instructions.