US 4,378,565 AGranted

Integrated circuit and method of making same

AssigneeGeneral Electric Company

InventorsMario Ghezzo, Ronald T. Jerdonek

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Abstract

An integrated circuit structure for reducing propagation delay is described. Integrated circuits include at least a pair of regions in each of which are located a respective plurality of functional cells and which are spaced apart by an interconnection region in which interconnection lines are provided connecting elements of the functional cells of one functional cell region with elements of the functional cells of the other functional cell region. Field oxide is provided in the interconnection region substantially greater in thickness than the field oxide in the regions of the functional cells thereby substantially reducing the capacitance and hence propagation delay of the interconnection lines. Formation of the field oxide of the interconnection region independent of the formation of the field oxide in the functional cell regions enables optimization of the field oxide in the interconnection region for minimum propagation delay without compromising functional cell formation in the functional cell regions.

An integrated circuit comprising:

a substrate of semiconductor material having a major surface,
a first surface adjacent region of said substrate containing a first part of said major surface,
a second surface adjacent region of said substrate spaced apart from said first surface adjacent region, said second surface adjacent region containing a second part of said major surface,
a third surface adjacent region contiguous to said first surface adjacent region and said second surface adjacent region, said third surface adjacent region containing a third part of said major surface,
a first plurality of thin layers of silicon dioxide, each thin layer overlying a respective first surface portion of said first surface adjacent region,
a second plurality of thin layers of silicon dioxide, each thin layer overlying a respective first surface portion of said second surface adjacent region,
a first thick layer of silicon dioxide overlying a second surface portion of said first surface adjacent region,
a second thick layer of silicon dioxide overlying a second surface portion of said second surface adjacent region,
a third thick layer of silicon dioxide overlying said third part of said major surface,
the thickness of said third thick layer of silicon dioxide being substantially greater than the thickness of said first and second thick layers,
a first plurality of functional cells formed in said first surface adjacent region, each overlying a respective first surface portion thereof,
a second plurality of functional cells formed in said second surface adjacent region, each overlying a respective first surface portion thereof,
a plurality of conductive lines interconnecting elements of the functional cells located in said first surface adjacent region with the elements of the functional cells located in said second surface adjacent region,
each of said conductive lines insulatingly overlying said third surface adjacent region.

11 more elements

Facts

Application

06/192,881Filed 1 Oct 1980

Granted

29 Mar 1983

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/495
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: capacitive…
H10P 14/61
Of insulating materials: using masks
H10W 10/0128
Using local oxidation of silicon [LOCOS]: comprising multiple local oxidation process steps
H10W 10/13
Isolation regions comprising dielectric materials: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation…

Abstract

Claims1