US 4,378,508 AGranted

EFL Logic arrays

AssigneeBell Telephone Laboratories, Incorporated

InventorRobert J. Scavuzzo

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Abstract

A logic gate is formed as a full 3-EFL circuit including a full two-level ECL current switch tree and an EFL stage made up of input and output multiemitter transistors. By appropriate connections, the logic gate may be used for a variety of circuits including a 4:1 multiplexer and a comparator of two three-digit binary numbers. The logic gate advantageously is formed in a silicon chip which includes an array of cells each consisting essentially of nine single-emitter transistors, two four-emitter transistors and a number, advantageously nine, of resistors.

Claims5

Dependent claims

A logic gate designed to provide an output function F which satisfies the Boolean expression

F=(a.sub.1 A+a.sub.2 A)C+(b.sub.1 B+b.sub.2 B)C
where a.sub.1, a.sub.2, b.sub.1, and b.sub.2 are input signals and A, B and C are control voltages comprising
means including an emitter coupled pair of transistors forming a first level differential amplifier, the first of said pair having its base connected to a terminal to which C is to be supplied and the second having its base connected to a terminal to be supplied with a first reference voltage, and each of the emitters being connected to current source means,
means including a pair of emitter-coupled pairs of transistors forming a second level pair of differential amplifiers, the first transistor of the first of the said second level pair having its base connected to a terminal to which A is to be applied, the second having its base connected to a terminal to be supplied with a second reference voltage, the collector of the first transistor of the first level pair being connected to the common emitter node of the first of the second level pairs of differential amplifiers, the first transistor of the other second level pair having its base connected to a terminal to which B is to be supplied and the second having its base connected to the terminal to be supplied with the second reference voltage, the collector of the second transistor of the first pair being connected to the common emitter node of this other second level pair,
a multiemitter input transistor having its first emitter connected to the collector of the first transistor of the first second level pair, its second emitter connected to the collector of the second transistor of the first second level pair, a third emitter connected to the collector of the first transistor of the other second level pair, and a fourth emitter connected to the collector of the second transistor of the other second level pair,
a plurality of terminals to be supplied separately with input signals a.sub.1, a.sub.2, b.sub.1, and b.sub.2, connected to the first, second, third, and fourth emitters, respectively, of said multiemitter transistor,
the base of said multiemitter transistor being connected to a terminal to be supplied with a third reference voltage,
and an output transistor having its base connected to the collector of the multiemitter transistor and to a pull-up resistor, its collector to a terminal to be supplied by a voltage supply, and its emitter connected to an output terminal where the output F is to be derived.

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Dependencies are inferred from the claim text.

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Abstract

A logic gate designed to provide an output function F which satisfies the Boolean expression

F=(a.sub.1 A+a.sub.2 A)C+(b.sub.1 B+b.sub.2 B)C
where a.sub.1, a.sub.2, b.sub.1, and b.sub.2 are input signals and A, B and C are control voltages comprising
means including an emitter coupled pair of transistors forming a first level differential amplifier, the first of said pair having its base connected to a terminal to which C is to be supplied and the second having its base connected to a terminal to be supplied with a first reference voltage, and each of the emitters being connected to current source means,
means including a pair of emitter-coupled pairs of transistors forming a second level pair of differential amplifiers, the first transistor of the first of the said second level pair having its base connected to a terminal to which A is to be applied, the second having its base connected to a terminal to be supplied with a second reference voltage, the collector of the first transistor of the first level pair being connected to the common emitter node of the first of the second level pairs of differential amplifiers, the first transistor of the other second level pair having its base connected to a terminal to which B is to be supplied and the second having its base connected to the terminal to be supplied with the second reference voltage, the collector of the second transistor of the first pair being connected to the common emitter node of this other second level pair,
a multiemitter input transistor having its first emitter connected to the collector of the first transistor of the first second level pair, its second emitter connected to the collector of the second transistor of the first second level pair, a third emitter connected to the collector of the first transistor of the other second level pair, and a fourth emitter connected to the collector of the second transistor of the other second level pair,
a plurality of terminals to be supplied separately with input signals a.sub.1, a.sub.2, b.sub.1, and b.sub.2, connected to the first, second, third, and fourth emitters, respectively, of said multiemitter transistor,
the base of said multiemitter transistor being connected to a terminal to be supplied with a third reference voltage,
and an output transistor having its base connected to the collector of the multiemitter transistor and to a pull-up resistor, its collector to a terminal to be supplied by a voltage supply, and its emitter connected to an output terminal where the output F is to be derived.

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