Emitter function logic latch and counter circuits
AssigneeBell Telephone Laboratories, Incorporated
InventorRobert J. Scavuzzo
Life of this patent
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Abstract
An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described.
Claims39
A latch circuit for receiving a data signal at an input terminal for storing the complement of said signal and for providing the complement at an output terminal, and having terminal means for coupling said latch circuit to a constant current source, to a first supply voltage, and to a second supply voltage comprising:
- a first transistor having a base coupled to the input terminal, a collector and an emitter;
- a second transistor having a base coupled to a first reference voltage, a collector coupled to the first supply voltage terminal, and an emitter coupled to the emitter of said first transistor;
- a third transistor having a base coupled to a second reference voltage, a collector, and at least a first emitter coupled to the collector of said first transistor and a second emitter;
- a resistive element coupled between said collector of said third transistor and a third reference voltage;
- and
- a fourth transistor having a base coupled to said collector of said third transistor, a collector coupled to the first supply voltage terminal, and at least a first emitter coupled to the second emitter of said third transistor, and a second emitter coupled to the output terminal.
A complementary data EFL latch for receiving a data signal and a clock signal at a data terminal and a clock terminal respectively, and for providing a complementary output of the input data at an output terminal comprising:
- a first and second npn single emitter transistor (SET) pair each having a base, a collector and an emitter connected in a differential configuration, having commonly coupled emitters, with the base of said first SET connected to the data terminal, the base of said second SET connected to a first reference voltage, and the collector of the second SET connected to a positive voltage terminal;
- a storage cell comprising a first and a second npn multi-emitter transistor (MET), the first emitter of said first MET connected to the collector of the first SET, the base of the first MET connected to a second reference voltage, the collector of the first MET connected to the base of the second MET and through a resistor to a third reference potential, the collector of the second MET connected to the positive supply voltage terminal, the first emitter of the second MET connected to the output terminal, the second emitters of the first and second METs connected together;
- and
- current steering means connected through a constant current source to a negative supply voltage terminal for providing a current path from the emitters of the first and second SETs or from the second emitters of the first and second METs depending upon the voltage of the clock terminal with reference to a fourth reference voltage.
A synchronous binary counter including a plurality of concatenated cells numbered 0 through n, wherein from 0.ltoreq.i.ltoreq.n, the i-th cell includes:
- a master latch having a data input, a control input, and an output Q.sub.i.sup.M, and being enabled by a first phase of a control signal C.sub.i applied to the control input to accept and store data and being latched during a second phase of C.sub.i ;
- a slave latch having a data input, a control input, and an output Q.sub.i providing an output for the cell, and being latched by the first phase of C.sub.i and being enabled by the second phase of C.sub.i ;
- one of the latches being an inverting latch and the other being a noninverting latch;
- means for coupling the output of the slave latch to the data input of the master latch;
- and means for coupling the output of the master latch to the data input of the slave latch;
- and
- means for interconnecting the cells such that
- C.sub.i =CLOCK+Q.sub.i-1.sup.M +Q.sub.i-2.sup.M. . . +Q.sub.1.sup.M +Q.sub.0.sup.M, where "CLOCK" indicates a count signal to be applied to the counter.
A counter as recited in claim 44 wherein, for at least one of the cells, the master latch includes a noninverting latch portion and an XOR function disposed in the coupling between the output of the slave latch and the noninverting latch portion of the master latch such that in response to the first state of the direction control signal applied to an input of the XOR function the master latch operates as an inverting latch, and in response to the second state of the direction control signal the master latch operates as a noninverting latch.
A counter as recited in claim 44 wherein, for at least one of the cells, the master latch includes an inverting latch portion and an XNOR function disposed in the coupling between the output of the slave latch and the inverting latch portion of the master latch such that in response to the first state of the direction control signal applied to an input of the XNOR function the master latch operates as an inverting latch, and in response to the second state of the direction control signal the master latch operates as a noninverting latch.
A counter as recited in claim 44, further adapted to count in BCD mode, comprising:
- means responsive to the direction control signal for providing, in response to the first state of the direction control signal, the logical OR of Q.sub.1 and Q.sub.3 to the data input of the master latch of the second state (i=1) and the logical OR of Q.sub.2 and Q.sub.3 to the data input of the third stage (i=2);
- an OR function means providing Q.sub.0 +Q.sub.1 +Q.sub.2 +Q.sub.3 at an output thereof;
- an inverting latch having a data input coupled to the output of the OR function;
- a control input and an output Q.sub.F, and being enabled by the first phase of C.sub.i applied to the control input and being latched by the second phase of C.sub.i ;
- and
- means responsive to the direction control signal for providing, in response to the second state of the direction control signal, the exclusive OR of Q.sub.1.sup.M and Q.sub.F to the data input of the slave latch of the second cell and the exclusive OR of Q.sub.2.sup.M and Q.sub.F to the data input of the slave latch of the third cell.
A counter as recited in claim 44, further including a direction control line and wherein the master latch in at least one of the cells includes:
- a master storage cell having a control input, a latch input, and an output providing Q.sub.i.sup.M ;
- a first current steering means having a first control input and a first pair of current paths for conducting current to a first common node, one of said paths being coupled to the latch input of the master storage latch;
- a second current steering means having a second control input and a second pair of current paths for conducting current to a second common node, the other of the paths of the first current steering means being coupled to the second common node;
- a third current steering means having a third control input and a third pair of current paths for conducting current to a third common node, the third common node being coupled to one of the paths of the second pair, and one of the paths of the third pair being coupled to the control input of the master storage cell;
- a fourth current steering means having a fourth control input and a fourth pair of current paths for conducting current to a fourth common node, the fourth common node being coupled to the other of the paths of the second pair, one of the paths of the fourth pair being coupled to the control input of the master storage cell, and the other of the paths of the fourth pair being coupled in common with the paths of the third pair to a terminal adapted to receive a supply voltage;
- the third and fourth control inputs being coupled either to the direction control line or to Q.sub.i ;
- the second control input being coupled to the output Q.sub.i if the third and fourth control inputs are coupled to the direction control line, or to the direction control line if the third and fourth control inputs are coupled to Q.sub.i ;
- and
- the first control input being coupled to C.sub.i.
Dependencies are inferred from the claim text.