US 4,377,855 A · Content-addressable memory

Abstract

A content-addressable memory (CAM) has an array of four-transistor memory cells arranged in rows corresponding to stored words and columns corresponding to a selected search word. Complementary column lines couple signals associated with the bits of the search word to the memory cells associated with all of the stored words in parallel. The memory cells of each row are coupled to a common sense line and cause a current to flow on the sense line in response to the search word not matching the data word associated with that row. Writing is accomplished by discharging one of the sense lines and applying signals representative of the desired word to be stored to the column lines. Since the ground lines are not unique to any row, they can be shared between adjacent rows or columns as best suits the layout of the circuit. A status bit is associated with each stored word and is used to selectively activate the sense amplifier associated with each row. The status bit is responsive to the signal on sense line and a separate control line, thus, simple comparisons can be used to selectively activate sense amplifiers. Finally, a unique control circuit associated with the most significant bit allows a selected segment of the content-addressable memory to be activated.

Claims12

Dependent claims

A content addressable memory having an array of memory cells comprising:

a first sense line associated with a first plurality of memory cells associated with a stored data word;
a ground line;
each memory cell comprising a first transistor coupled to the sense line and a second transistor serially coupled between the first transistor and the ground line, a third transistor coupled to the sense line and a fourth transistor serially coupled between the third transistor and the ground line, wherein the node between the first and second transistors is coupled to the gate of the fourth transistor and the node between the third and fourth transistors is coupled to the gate of the second transistor;
first and second compare line means for providing compare signals in response to a data bit of an address to be compared to the stored data word, the first compare line means coupled to the gate of the first transistor and the second compare line means coupled to the gate of the third transistor;
and
means for providing a match signal in response to sensing no current on the first sense line.

3 more elements

Dependencies are inferred from the claim text.

Content-addressable memory

Life of this patent

Content-addressable memory

Life of this patent

Abstract

Claims12