US 4,377,849 AGranted

Macro assembler process for automated circuit design

AssigneeInternational Business Machines Corporation

InventorsWesley C. Finger, Gerald B. Long

Life of this patent

Estimating the term…

Loading patent…

Abstract

A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.

Claims4

Dependent claims

A multipass process for automatically generating topologies for fabricating large scale integrated circuits comprising the steps of:

(a) inputting electrical and functional data relative to the logic technology used;
(b) calculating a logical map of the desired logic function;
(c) designing a plurality logic cells representative of functional logic components;
(d) dividing said plurality of logic cells into a plurality of basic cell components having a plurality of common elements;
(e) selecting said basic cell components in accordance with the calculated logical map of the desired logic function;
(f) concatenating the selected basic cell components into a plurality of intermediate level cells representing components of the desired logic function, and
(g) concatenating said plurality of intermediate cells into a prime cell representing desired logic function.

4 more elements

Dependencies are inferred from the claim text.