Threshold referenced MNOS sense amplifier

In a transistor memory array disposed in bit line columns and wordline rows comprising metal nitride oxide semiconductor field effect transistors (MNOS) wherein the organization of the array is such that the array comprises means for single-element-per-bit storage and two-element-per-bit sensing wherein the sensing means compares a threshold voltage of a single MNOS contained within an MNOS bit line column of the memory array to the threshold voltage of a single reference transistor contained within a column of such reference transistors wherein the MNOS column and the reference transistor column are substantially in electrical balance during the operation of the sensing means, wherein each MNOS bit line column is connected to the sensing means by a separate decoding means wherein the decoding means effectively isolates the column from the remainder of the array and where that portion of the array underlaying the MNOS transistors is underlain by an isolation tub connected to a control circuit,

• a method of operating the array wherein the threshold voltage level of at least one of the MNOS transistors in a single word line row is changed from one state to another state.

In a transistor memory array disposed in bit line columns and wordline rows comprising metal nitride oxide semiconductor field effect transistors (MNOS) wherein the organization of the array is such that the array comprises means for single-element-per-bit storage and two-element-per-bit sensing wherein the sensing means compares a property of a single MNOS contained within an MNOS bit line column of the memory array to the same property of a single reference transistor contained within a column of such reference transistors wherein the MNOS column and the reference transistor column are substantially in electrical balance during the operation of the sensing means,

• a method of operating the array wherein the sensing means utilizes a ramped interrogation voltage pulse in its comparison of the threshold voltage of the MNOS device and the threshold voltage of the reference transistor wherein a substantial portion of the pulse has a voltage level below that of the threshold voltage of the reference transistor.

In a transistor memory array disposed in bit line columns and word line rows comprising metal nitride oxide semiconductor field effect transistors (MNOS), the improvement comprising:

• an organization of the array such that the array comprises means for single-element-per-bit storage and two-element-per-bit sensing wherein the sensing means compares a property of a single MNOS transistor in an MNOS bit line column of the array to the same property of a single reference transistor contained within a column of such reference transistors wherein the MNOS column and the reference transistor column are substantially in electrical balance during the operation of the sensing means,
• wherein the array is organized into two sub-arrays, the two sub-arrays having an equal number of MNOS bit line columns and each sub-array having one reference MOS column, the array being symmetric about a central axis with the two MOS reference columns disposed closest to the axis.

In a transistor memory array disposed in bit line columns and word line rows comprising metal nitride oxide semiconductor field effect transistors (MNOS), the improvement comprising:

• an organization of the array such that the array comprises means for single-element-per-bit storage and two-element-per-bit sensing wherein the sensing means compares a property of a single MNOS transistor in an MNOS bit line column of the array to the same property of a single reference transistor contained within a column of such reference transistors wherein the MNOS column and the reference transistor column are substantially in electrical balance during the operation of the sensing means,
• wherein each reference transistor column is connected to the sensing means by a separate transistor wherein the drain electrode of the transistor is connected in common to all of the source electrodes of the reference transistors in the column, the source electrode of the transistor is connected to the sensing means, and the gate electrode of the transistor is connected to a control circuit.

In a transistor memory array disposed in bit line columns and word line rows comprising metal nitride oxide semiconductor field effect transistors (MNOS), the improvement comprising:

• an organization of the array such that the array comprises means for single-element-per-bit storage and two-element-per-bit sensing wherein the sensing means compares a property of a single MNOS transistor in an MNOS bit line column of the array to the same property of a single reference transistor contained within a column of such reference transistors wherein the MNOS column and the reference transistor column are substantially in electrical balance during the operation of the sensing means,
• wherein a word line row comprises a plurality of individual MNOS devices located in a row of the array, the gate electrodes of the MNOS devices being connected in common to a control circuit and further connected in common to the corresponding reference transistor through means which produce an offset condition in the property compared by the sensing means between the MNOS device and the reference transistor.