Double Lambda diode memory cell
AssigneeBurroughs Corporation
InventorsMohamed I. Elmasry, LuVerne R. Peterson
Life of this patent
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Abstract
Disclosed is an improved static memory cell comprised of first and second conductive means for carrying respective bias voltages in the cell, a third conductive means for carrying an input/output voltage signal in the cell, and a Lambda diode coupled between the first and third conductive means for there providing a negative dynamic resistance whenever the input/output voltage signal is within a predetermined range between the bias voltages on the first and second conductive means, with the improvement being a voltage dependent resistance means coupled between the second and third conductive means for there providing a negative dynamic resistance in response to at least some of the input/output voltages within said range.
Claims9
An improved memory cell comprised of:
- first and second conductive means for carrying respective bias voltages in said cell;
- a third conductive means for carrying an input/output voltage signal in said cell;
- a Lambda diode coupled between said first and third conductive means for there providing a negative dynamic resistance whenever said input/output voltage signal is within a predetermined range between said bias voltages on said first and second conductive means;
- wherein the improvement comprises a voltage dependent resistance means coupled between said second and third conductive means for there providing a negative dynamic resistance in response to at least some of said input/output voltages within said range.
An improved cell comprised of:
- first and second conductive means for carrying respective bias voltages in said cell;
- a third conductive means for carrying an input/output voltage signal in said cell;
- wherein the improvement comprises a first voltage dependent resistive means coupled between said first and third conductive means and a second voltage dependent resistive means coupled between said second and third conductive means for providing between their respective conductive means a negative dynamic resistance for some range of input/output voltage signals on said third conductive means which lies within the bias voltage on said first conductive means and the bias voltage on said second conductive means.
Dependencies are inferred from the claim text.