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US 4,376,985 AGranted
Semiconductor memory device
AssigneeFujitsu Limited
InventorHideaki Isogai
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device including memory cells, formed by a pair of multi-emitter transistors each having a collector and a base which are cross connected to each other and arranged in row and column directions, and read-out transistors, each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, wherein the read-out transistors are arranged in each column. The multi-emitter transistors and the read out transistors are formed in patterns and the characteristics of both the multi-emitter and read-out transistors have the same variation due to a dispersion of the patterns caused by the manufacturing process.
Claims10
A semiconductor memory device comprising:
- an isolation region having a plurality of portions;
- memory cells, each comprising a pair of multi-emitter transistors each having a collector and a base which are cross-connected to each other and each being surrounded by one of the plurality of portions of said isolation region, said memory cells arranged in row and column directions;
- and
- read-out transistors, each having a base and an emitter which is commonly connected to one of the emitters of said multi-emitter transistors, arranged in each column, each of said read-out transistors being surrounded by one of the plurality of portions of said isolation region, each of said pair of multi-emitter transistors formed such that the relative position of said one of the emitters of said multi-emitter transistor, which is commonly connected to the emitter of one of said read-out transistors, to its base and the isolation region is the same as the relative position of said emitter, of said one of said read-out transistors, to its base and the isolation region, so that the characteristics of both the multi-emitter transistors and the read-out transistors have the same variation.
1 more element
A semiconductor memory device comprising:
- an isolation region having first through sixth portions;
- first, second, third and fourth bit lines;
- a first memory cell operatively connected to said first and second bit lines;
- a second memory cell operatively connected to said third and fourth bit lines, said first and second memory cells arranged in a row;
- a first read-out transistor having a first emitter operatively connected to said first bit line, having a second emitter operatively connected to said third bit line, having a base and having a collector, said first read-out transistor being surrounded by the first portion of said isolation region;
- and
- a second read-out transistor having a first emitter operatively connected to said second bit line, having a second emitter operatively connected to said fourth bit line, having a base and having a collector, said second read-out transistor being surrounded by the second portion of said isolation region;
- said first memory cell comprising first and second multi-emitter transistors each having a collector and a base which are cross-connected to each other, said first multi-emitter transistor surrounded by the third portion of said isolation region and having a first emitter connected to said first bit line, said second multi-emitter transistor surrounded by the fourth portion of said isolation region and having a first emitter connected to said second bit line;
- said second memory cell comprising third and fourth multi-emitter transistors each having a collector and a base which are cross-connected to each other and each having an isolation region, said third multi-emitter transistor surrounded by the fifth portion of said isolation region and having a first emitter connected to said third bit line, said fourth multi-emitter transistor surrounded by the sixth portion of said isolation region and having a first emitter connected to said fourth bit line;
- said first and second multi-emitter transistors formed such that the relative positions of said isolation region to said first emitter and said base in said first and second multi-emitter transistors are the same as the relative positions of said isolation region to said first emitter and said base in said first and second read-out transistors, respectively, so that the characteristics of said first and second multi-emitter transistors and said first and second read-out transistors, respectively, have the same variation.
7 more elements
Dependencies are inferred from the claim text.