Computer system with scannable program memory

A computer system comprising as subsystems:

• a. a program memory having a sequence of address locations for storing respective machine code data;
• b. a keyboard;
• c. a display device for displaying at least one row of alphanumeric characters;
• d. a processor:
• and interconnecting means for interconnecting said subsystems;
• wherein said processor contains at least:
• an address register having an increment input for addressing the program memory;
• an instruction register having op code storage means (205) and further storage means (207, 256) for together storing an instruction of at most a predetermined length, said instruction register having an instruction input for coupling to an instruction output of said program memory;
• first and second instruction decoder means connected to instruction outputs of said opcode storage means and said further storage means, respectively;
• an execution element having a control input connected to a control output of said first instruction decoder for executing a data processing operation;
• an address distance detector for detecting a predetermined address distance as traversed in said program memory, the maximum range of said address distance being longer than corresponds to an address distance covered in completely filling said instruction register, said address distance detector having an activation input connected to an activation output of said first instruction decoder for receiving an activation signal under control of a first opcode subset (110001xx) detected, and for thereupon receiving via first means (209) from the instruction register a first address distance to be covered in the program memory and then generating a first control signal (296);
• wherein said address distance detector has second means (298) for monitoring a relative address distance as covered in the program memory after reception of said activation signal and upon reaching said first address distance generating a deactivation signal (304) and terminating said first control signal;
• and wherein said processor is responsive to said first control signal for being driven into a non-active mode for information received from the program memory thereof until generation of said deactivation signal.