Overlapped macro instruction control system

In a digital data processing system having an instruction repertoire including a plurality of macro instructions which can be programmably selected and sequenced, wherein the execution of each macro instruction is under the control of a predetermined associated set of micro instructions, each of said micro instructions for controlling a predetermined portion of the execution of the macro instructions, a main memory device for storing data words and programmed macro instructions in a sequence for operation, and an arithmetic processor for executing the programmed sequence of macro instructions in accordance with the sets of micro instructions associated with each of said macro instructions, and control apparatus coupled to said main memory device and for providing timing and control signals, macro instruction overlap control apparatus coupled to said control apparatus and said arithmetic processor comprising:

• first and second addressable control store means, each adapted for storing the sets of micro instructions for controlling the execution of the repertoire of macro instructions;
• input means for providing a first group of signals indicative of the macro instructions to be executed, and coupled to said first and second addressable control store means for providing a second group of signals indicative of the entry addresses in said first and second addressable control store means for the set of micro instructions associated with said macro instructions;
• overlap control means coupled to said input means and including addressable overlap control count storage means adapted for storing control count words for each sequence of macro instructions in the repertoire of the instructions of the macro instructions defining the operations that must be completed before the next sequential macro instruction can be allowed to proceed, and and macro instructions sequence determining means coupled to said input means for providing macro instructions sequence determining signal for addressing said overlap control count storage means;
• cycle counter means coupled to said first and second addressable control store means for counting the number of micro instructions executed and providing a first cycle count in relationship to said first addressable control store means and a second cycle count in relationship to said second addressable control store means;
• micro instruction execute means coupled to said first and second addressable control store means for providing micro instructions to said processor, including a gate means for receiving enabling gate signals for controlling loading of said micro instructions execute means from said first addressable control store means, or said second addressable control store means, or both said first and second addressable control store means;
• cycle count comparison means coupled to said cycle counter means and said overlap count control storage means for comparing said control count words to the count of execution of micro instructions for the one of said first and second addressable control store means in control of macro instructions operation for providing said enabling gate signals to said micro instruction execute means when said control count words have a predetermined relationship to the number of micro instructions executed, thereby providing for simultaneously executing micro instructions for the last macro instruction and the current macro instruction.

In a digital data processing system having a data processor unit for executing programmed ones of a repertoire of macro instructions, each macro instruction defined by an associated set of micro instructions for controlling the functions of the data processor, a main memory unit for storing macro instructions and data words, a control unit intermediate the data processor unit and main memory unit for controlling transfer of programmed macro instructions and data words and providing timing for execution of one micro instruction per clock cycle and control signals, said control unit including macro instruction overlap control apparatus comprising:

• first and second addressable control store means, each adapted for storing all of the sets of micro instructions associated with the executions of the repertoire of macro instructions;
• first input means for receiving instruction signals indicative of the macro instruction to be executed;
• second input means coupled to said first and second addressable control store means for receiving address signals indicative of the entry address of the set of micro instructions associated with said macro instructions to be executed, and applying said address signals to said first and second addressable control store means;
• third input means coupled to said first and second addressable control store means for receiving control signals for selectively activating one of said first and second addressable control store means for executing a macro instruction;
• overlap control means including addressable overlap control count storage means adapted for storing control count words for each sequence of occurrence of macro instructions defining the number of micro instructions of the then current macro instruction that must be executed before the next macro instruction can commence, each of said control count words including a data dependency indicating bit for providing data dependency indicating signals indicating whether the first macro instructions in the sequences of macro instructions are variable in the number of micro instructions sequences depending on evaluation of data, and macro instruction combining means coupled to said first input means and said overlap control count storage means for accessing the associated control count word for the sequence of macro instructions;
• cycle counter means for counting the number of micro instructions read and executed from each of said first and second addressable control store means;
• cycle count comparison means coupled to said cycle counter means and said overlap control count storage means for comparing the control count words to the count of micro instructions executed for providing enabling signals when a predetermined relationship is determined to exist;
• micro instructions execution means coupled to said first and second addressable control store means for receiving micro instructions therefrom and transmitting said micro instructions to control the processor and including overlap enabling means coupled to said cycle count comparison means for simultaneously receiving micro instruction from both of said first and second addressable control store means when said enabling signal is present, thereby providing for simultaneous execution of micro instructions from two different macro instructions;
• and
• variable sequence control means coupled to said overlap control means for receiving said data dependency indicating signals indicating that the related macro instructions is of a variable sequence dependent upon the data, and having means for receiving signals indicative that the variable portion of the sequence has been completed, said variable sequence control means coupled to said cycle counter means for inhibiting advancement of the counting operation until the end of variable sequence signal has been received.