US 4,376,972 AGranted

Sequential word aligned address apparatus

AssigneeHoneywell Information Systems Inc.

InventorsRobert B. Johnson, Chester M. Nibby, Jr., Dana W. Moore

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Abstract

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

Claims41

Dependent claims

A memory subsystem for use in a system including a processing unit coupled to a multiword bus in common with said subsystem for transfer of information therebetween during bus transfer cycles of operation, said unit being operative to generate memory requests on said bus to said subsystem, each of said requests include a multibit address containing row and column addresses, said memory subsystem comprising:

a plurality of independently addressable memory module units, each memory unit being individually coupled to said multiword bus and having a set of input address lines, said each memory unit including a plurality of rows of random access memory chips and said random access memory chips including a predetermined number of addressable arrays of memory storage devices, said arrays being divided into a predetermined number of rows and columns;
address register means for storing a plurality of least significant address bits of each said address;
first and second multibit tri-state register means coupled to said bus for storing row and column addresses respectively of each said memory request address and said first and second register means being connected in common with said set of lines of said memory module units;
increment circuit means being connected in series with the least significant address lines of said set of address lines of a predetermined one of said memory module units;
and
logic circuit means coupled to said address register means and to said increment circuit means;
said logic circuit means being operative to condition said increment circuit means to modify the portion of said row address applied to said least significant address lines only as a function of the coding of said plurality of least significant address bits enabling simultaneous access to a plurality of sequential storage locations within said predetermined number of said addressable arrays of said memory module units during a single bus cycle of operation.

4 more elements

A memory subsystem for use in a system including a processing unit coupled to a multiword bus in common with said subsystem for transfer of information therebetween during bus transfer cycles of operation, said unit being operative to generate memory requests on said bus to said subsystem, each of said requests include a multibit adddress coded to specify a storage location with memory subsystem to be accessed, said memory subsystem comprising:

a pair of independently addressable memory module units, each memory unit being individually coupled to said multiword bus and having a set of address input lines, said each memory unit including a plurality of rows of random access memory chips and said random access memory chips including a number of addressable arrays of memory storage devices, said arrays being divided into a number of rows and columns;
addressing means coupled to receive said multibit address of each memory request, said addressing means including:
a multibit address register for storing the least significant address bits of each said memory request address for the duration of processing by said subsystem;
first and second multibit tri-state registers, each having inputs and outputs, said inputs of said first and second registers being coupled to said bus to store row and column address portions respectively of each said memory request address and corresponding ones of said outputs of said first and second registers being connected in common with said sets of address lines;
an adder circuit being connected in series with the least significant address lines of said address input lines of a predetermined one of said memory module units;
and
logic circuit means coupled to said multibit address register and to said adder circuit, said logic circuit means being operative to condition said adder circuit to increment by one the row address signals applied to said least significant address lines as a function of the coding of said least significant address bits enabling simultaneous access to a pair of words from sequential storage locations within said number of addressable arrays of said memory module units during a single bus cycle of operation.

4 more elements

A memory subsystem for use in a system including a processing unit coupled to a multiword bus in common with said subsystem for transfer of data words therebetween during bus cycles of operation, said unit being operative to generate memory requests on said bus to said subsystem, each of said requests including a multibit address having row and column addresses coded to specify a storage location within said memory subsystem to be accessed, said subsystem comprising:

a plurality of independently addressable memory module units, each memory unit being individually coupled to a different word section of said multiword bus and having a set of address input lines, said each memory unit including a plurality of rows of random access memory chips for providing storage of data words, one module unit including the even numbered rows containing storage locations having even addresses and the other module unit including the odd numbered rows containing storage locations having odd addresses, said random access memory chips including a number of addressable arrays of memory storage devices, said arrays being divided into a number of rows and columns;
an address register for storing a plurality of least significant address bits of each said memory request address;
first and second multibit tri-state address registers each having inputs and outputs, a number of said inputs of said registers being coupled to said bus for storing said row and column addresses respectively and corresponding ones of said outputs of said first and second registers being connected in common with said sets of address lines;
an adder circuit being connected in series with the least significant address lines of said address input lines of said memory module unit containing data words having said even addresses;
timing means for generating a predetermined sequence of timing signals in response to each said memory request, said timing means being coupled to predetermined inputs of said first and second tri-state registers, said first and second tri-state registers being conditioned by a first one of said sequence of timing signals applied to said predetermined inputs to apply in succession said row and column addresses to said outputs and said plurality of memory module units being conditioned by a plurality of row address strobe timing signals and a column address strobe timing signal of said sequence to store said row and column addresses in succession in even and odd rows of said random access memory chips specified by said least significant address bits;
and,
logic circuit means coupled to said multibit address register, to said adder circuit and to said timing means, said logic circuit means being operative in response to another one of said sequence of timing signals to condition said adder circuit to increment by one, the row address applied to said least significant address lines as a function of the coding of said least significant address bits enabling simultaneous access to a plurality of even and odd sequential word locations within said number of said addressable arrays of said memory module units during a single bus cycle of operation.

4 more elements

N number of independently addressable memory module units, each memory unit being individually coupled to a different word section of said multiword bus and having a set of address input lines, said each memory unit including a plurality of rows of random access memory chips for providing storage of data words, N/2 module units including the even numbered rows containing storage locations having even addresses and N/2 module units including the odd addresses, said random access memory chips including a number of addressable arrays of memory storage devices, said arrays being divided into a number of rows and columns;
an address register for storing a plurality of least significant address bits of each said memory request address;
first and second multibit tri-state address registers each having inputs and outputs, a number of said inputs of said registers being coupled to said bus for storing said row and column addresses respectively and corresponding ones of said outputs of said first and second registers being connected in common with said sets of address lines;
N-1 number of adder circuits being connected in series with the least significant address lines of said address input lines of said N/2 memory module units contining data words having said even addresses and (N/2)-1 memory module units containing data words having said odd addresses;
and,
N-1 number of logic circuit means, each logic circuit means being coupled to said multibit address register and to a corresponding one of said N-1 adder circuits, said N-1 logic circuit means being operative to condition said adder circuits to increment by one, the portion of said row address applied to said least significant address lines as a function of the coding of said plurality of least significant address bits enabling simultaneous access to a plurality of even and odd sequential word locations within said number of said addressable arrays of said memory module units during a single bus cycle of operation.

3 more elements

Dependencies are inferred from the claim text.