US 4,375,693 AGranted

Adaptive sweep bit synchronizer

AssigneeFord Aerospace & Communications Corporation

InventorWilliam B. Kuhn

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Abstract

A partly analog partly digital bit synchronizer capable of acquisition and operation over an arbitrarily broad range of data rates is disclosed. A second order phase lock loop (PLL) is employed providing both phase and frequency correction to a voltage controlled oscillator (VCO). The phase detector consists of a binary counter whose most significant bit (MSB) is defined to be the recovered clock. The desired data transition points are defined as coinciding with the falling edge of the counter's MSB. At each data transition, the least significant bits within the counter are used to set the duration of phase and frequency correction pulses proportional to the phase error, which pulses are then fed to the VCO. An acquisition circuit diverts the frequency correction pulses in order to sweep the VCO within a selected half octave. Lock is recognized when a preselected number of data transitions with phase error below a preset maximum occur consecutively. An autorange capability automatically steps the frequency through half octaves within an arbitrarily large range.

Claims6

Dependent claims

A bit synchronizer for generating a recovered clock output in synchronization with an input data stream containing random antipodal data, comprising:

phase detector means for measuring phase differentials between transitions within said input data stream and said recovered clock, said detector means having a first input coupled to the input data bit stream, and two outputs, i.e., a phase error signal and the recovered clock;
means for monotonically varying the frequency of said recovered clock over a preselected range prior to synchronization, said varying means having a first input coupled to the phase error signal and an output coupled to a second input of the phase detector means;
and
means for deciding when said input data stream and said recovered clock are in synchronization, said deciding means having a first input coupled to the input data stream, a second input coupled to the phase error signal, and an output coupled to a second input of the varying means;
wherein the varying means has a third input coupled to the input data stream, and the rate of varying the frequency of the recovered clock depends upon the data rate and transition density of the input data stream.

2 more elements

Dependencies are inferred from the claim text.