Redundant memory arrangement providing simultaneous access
AssigneeSperry Corporation
InventorRobert H. Krebs, Jr.
Life of this patent
Estimating the term…
Abstract
A memory system for a data processing apparatus including a stack and a stack image memory which provides either sequential or simultaneous access to information contained on the stack. A stack control logic unit is responsive to a stack instruction so that information written into the stack is simultaneously written into one or more random access memory units. Moreover, a sequence of information items read sequentially from the stack may be read simultaneously from different random access memory units. The memory address unit is preferably implemented with programmable read-only memories.
Claims21
A memory system for data processing apparatus including a stack, comprising:
- a logical functional unit having an input for receiving operands for performing stack operations, and an output;
- data bus means coupled to the output of said functional unit;
- stack memory means coupled to said data bus means for storing successive items of information on said data bus means in the form of a stack of sequentially accessible items;
- stack image memory means coupled to said data bus for storing said successive items of information in the form of an array of simultaneously accessible items;
- said stack image memory means comprises a plurality of substantially identical random access memory circuits;
- and
- memory address means connected to each of said random access memory circuits for providing respective addresses to each of said random access memory circuits for storing each of said items of information.
A data processing system comprising,
- first memory means for storing a set of information words;
- said first memory means having a first operating mode of accessing said information words stored therein;
- a plurality of second memory means;
- each of said second memory means storing said set of information words and having a second operating mode of accessing said information words stored therein;
- addressing means operatively connected with each of said second memory means for accessing predetermined selected ones of said information words in each of said second memory means;
- each of said accessed information words being provided on a respective output of each of said second memory means;
- and
- register means connected to all of said respective outputs of each of said second memory means so as to store and concatenate said accessed information words as a single register word.
A data processing system comprising
- a first memory module for storing a plurality of items of information having a first data structure;
- a plurality of substantially identical second memory modules,
- each of said second modules storing said items of information having a second data structure different from said first data structure;
- data input/output means connected to said first memory module for transferring said items of information thereto and therefrom;
- tracking logic means connected to said first memory module and responsive to the transfer of one of said items of information to produce an enabling signal;
- and
- access means connected to said second modules and responsive to said enabling signal to perform a corresponding transfer of corresponding items of information stored in respective ones of said second modules.
Dependencies are inferred from the claim text.