Semiconductor device and a method of producing the same

A semiconductor memory device having plural elementary regions on a semiconductor substrate selectively isolated by V-shaped grooves, said semiconductor device comprising

• a first semiconductor layer of a first conductivity type formed over said substrate,
• an insulating layer selectively covering the surface of said first semiconductor layer, with predetermined portions of said insulating layer being enlarged in thickness, and respective ones of said predetermined portions essentially surrounding a central portion of each said elementary region,
• an injector region of the opposite conductivity type formed in said central portion of each said elementary region essentially under said insulating layer to be essentially surrounded by the respective thicker portions of said insulating layer of the elementary region,
• at least two regions of the opposite conductivity type in each elementary region, located selectively between said thicker portions of said insulating layer and said V-shaped grooves of the respective elementary region, and
• at least one region of the first conductivity type located in each one of said at least two regions of the opposite conductivity type,
• wherein said V-shaped grooves surround each said elementary region and include deep V-shaped grooves aligned in a first direction and shallow V-shaped grooves aligned transversely thereto, said deep V-shaped grooves extending through said first semiconductor layer, and said shallow V-shaped grooves terminating before reaching said substrate, so that selected corresponding portions in adjacent pairs of said elementary regions in said first direction are isolated while other selected corresponding portions of adjacent pairs of said elementary regions in the transverse direction are commonly connected as a result of said termination of said shallow V-shaped grooves, and
• where the bottom of said thick oxide portions are below the top surface of the adjoining semiconductor regions, and
• wherein each said elementary region includes a pair of vertical bipolar transistors comprising respective ones of said at least two regions of opposite conductivity type and the respective at least one region of the first conductivity type in each said region of the opposite conductivity type.