Synchronous bus arbiter

Abstract

A bus arbitration arrangement for resolving competing requests for access to a bus is associated with local signal control lines, that are coupled to its associated "master" (i.e. user of the bus), and control lines of the bus common to all other units. These local signal control lines include a set of identification lines defining the address (and priority rank) of the associated master, a request line through which the master requests access to the bus, a grant line through which a master is informed that it has control of the bus, and a release line through which the master informs the bus exchange control circuit that it is releasing its control of the bus. Control lines which are common to other units on the bus include a busy line, through which each interface circuit is advised that the bus is currently in use, a bus clock line for synchronizing the operation of the bus exchange control circuits, a set of bus request lines over which the addresses of users requesting control of the bus are conveyed and through which priority among conflicting requests is resolved, and a select acknowledgement line which is used to terminate priority resolution once it has been determined which requesting user has highest priority. The bus exchange control circuit itself contains a set of combinational logic, which carries out a set of housekeeping chores using the control signal lines, so as to enable its associated master to gain control of the bus when requested and, in the event of a plurality of simultaneous requests, resolving those requests in favor of the master whose identification lines indicate the highest priority among potential users of the bus.

Dependencies are inferred from the claim text.