Signal measurement apparatus
AssigneeTektronix, Inc.
InventorsChon H. Leow, Toshihisa Nagai
Life of this patent
Estimating the term…
Abstract
A word recognizer probe to be removably incorporated with the mainframe of a logic analyzer is disclosed. The use of serial input-parallel output type memory means in the probe minimizes the number of interconnection signal paths between the probe and the mainframe regardless of the input bits to be recognized.
Claims15
A signal measurement apparatus for measuring an input signal in response to a selected logic combination of n-channel parallel logic input signals, comprising:
- a mainframe for receiving said input signal to be measured, said mainframe including a clock generator for generating a clock signal and means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination;
- and
- a subframe including serial input-parallel output type logic memory means and comparison means;
- said memory means receiving said clock signal and said serial logic signal from said mainframe for converting said serial logic signal into an n-bit parallel logic signal;
- said comparison means comparing said n-bit parallel logic signal from said memory means with said n-channel parallel logic input signals and generating an output signal when a combination of said n-channel parallel logic input signals corresponds to said logic combination set by said mainframe;
- wherein said output signal from said comparison means is supplied to said mainframe for controlling the operation of said mainframe.
A logic analyzer for measuring one or more logic input signals in response to a selected logic combination of n-channel parallel logic input signals, comprising:
- a mainframe for receiving said logic input signals to be measured, said mainframe including a clock generator for generating a clock signal and setting means for generating a single serial logic signal consisting of n bits in synchronism with said clock signal to set said logic combination;
- a word recognizer including serial input-parallel output type logic memory for converting said serial logic signal into an n-bit parallel logic signal and comparison means for generating an output when a combination of said n-channel parallel logic input signals corresponds to a combination of said parallel logic signal from said memory means;
- and
- interconnection means for connecting said word recognizer to said mainframe;
- said interconnection means including conductors for supplying power voltage, reference level, said serial logic signal, said clock signal, and said output signal.
Dependencies are inferred from the claim text.