Signal stability recognition
AssigneeBeckman Instruments, Inc.
InventorJames G. Van Vliet
Life of this patent
Estimating the term…
Abstract
Apparatus for indicating when an analog or digital input signal remains sufficiently stable for a predetermined length of time. The apparatus continuously monitors the input signal instead of sampling it only at discrete points in time. The apparatus includes a memory which stores the value of the input signal at the time of the most recent occurrence of a reset signal, a comparator which produces the reset signal whenever the input signal differs from the memory signal by an amount greater than that allowed by a predetermined comparison criterion, and a timer for indicating that the input signal is stable when the reset signal has not been produced for a time exceeding the predetermined length of time.
Claims4
Apparatus for indicating when an input signal remains sufficiently stable for a predetermined length of time, comprising:
- memory means, responsive to the input signal and a reset signal, for producing a memory signal equal to the value of the input signal at the time of the most recent occurrence of the reset signal;
- comparator means responsive to the memory signal and to the input signal for producing the reset signal when the input signal differs from the memory signal by an amount greater than that allowed by a predetermined comparison criterion;
- and
- resettable timing means responsive to the reset signal for indicating that the input signal is stable by generating a signal only when the reset signal has not been produced for a time exceeding the predetermined length of time.
Apparatus for indicating when a digital input signal remains sufficiently stable for a predetermined length of time, comprising:
- memory means, responsive to the digital input signal and to a reset signal, for producing a digital signal equal to the value of the digital input signal at the time of the reception of the reset signal by the memory means;
- comparator means including means for determining when the difference between the digital input signal and the digital memory signal exceeds a predetermined number of binary counts, and means for generating the reset signal when the difference exceeds the predetermined number of binary counts;
- and
- resettable timing means for generating a signal only when the reset signal has not been produced for a time exceeding the predetermined length of time to thereby indicate that the input signal is sufficiently stable.
Dependencies are inferred from the claim text.