Sense amplifier for integrated memory array
AssigneeInternational Business Machines Corporation
InventorPhilip T. Wu
Life of this patent
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Abstract
A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.
Claims7
In a memory array having a bit line connected to a set of storage cells, and having a source for producing at least one clock phase during a portion of a storage cycle of said memory array, a sense amplifier comprising:
- a depletion FET of a predetermined channel polarity and having a source coupled to said bit line, a drain coupled to a sense node, and a gate connected directly to a ground potential;
- and
- a further FET of the same predetermined channel polarity and having a source coupled to said sense node, a drain coupled to a compatible supply potential, and a gate connected to receive said one clock phase so as to switch said further FET both on and off during said storage cycle.
In a memory array having first and second bit lines connected to first and second sets of storage cells, and having a source for producing multiple clock phases during a storage cycle of said memory array, a sense amplifier comprising:
- first and second depletion FETs each of the same predetermined channel polarity and having a source connected to one of said bit lines, a drain connected to one of first and second sense nodes, and a gate connected directly to a ground potential;
- third and fourth FETs each of said same predetermined channel polarity and having a source connected to one of said sense nodes, a drain connected to a compatible supply potential, and a gate connected to a first of said clock phases;
- and
- fifth and sixth FETs each having a source connected to a second of said clock phases, a drain connected to one of said sense nodes, and a gate connected to an opposite one of said sense nodes so as to form a latch circuit.
Dependencies are inferred from the claim text.