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US 4,375,087 AGranted
Electrically erasable programmable read only memory
AssigneeHughes Aircraft Company
InventorFrank M. Wanlass
Life of this patent
Estimating the term…
Abstract
A floating gate tunneling metal oxide semiconductor (FATMOS) transistor is formed in a well region on a semiconductive substrate of a conductivity type opposite to that of the well region, so that charging and discharging of the FATMOS floating gate is accomplished by controlling the potential of the well region. As a result, in an electrically erasable programmable read-only memory, each memory cell requires only one FATMOS transistor, the need for an additional control transistor having been eliminated. Selection of individual memory cells is enhanced by providing a floating gate which only partially overlies the FATMOS transistor channel, so that the overlying FATMOS control electrode performs an "and" gate function independently of the floating gate.
Claims20
An electrically erasable and programmable transistor, comprising:
- a semiconductor substrate;
- a source and a drain defining a channel region therebetween in said substrate;
- an insulated floating gate at least partially overlying said channel region;
- a dielectric film between said floating gate and said substrate, said film having a thin tunneling region overlying said channel region;
- a control gate overlying said floating gate and spanning said channel region, said control gate insulated from said floating gate and from said substrate;
- and
- means for setting the potential of said channel region to be sufficiently more attractive to electrons than the potential of said overlying control gate so as to cause electrons to tunnel from said floating gate to said channel region, and for setting said channel region potential to be sufficiently less attractive so as to prevent electrons from tunneling from said floating gate to said channel region and allow electrons to tunnel from said channel region to said floating gate.
4 more elements
An electrically erasable and programmable transistor, comprising:
- a semiconductive substrate of a first conductivity type;
- a well region in said substrate of a second conductivity type;
- a source and a drain of said first conductivity type inside said well region defining a channel region therebetween;
- an insulated floating gate at least partially overlying said channel region;
- a dielectric film between said floating gate and said substrate, said film having a thin tunneling region overlying said channel region;
- a control gate overlying said floating gate and spanning said channel region, said control gate insulated from said floating gate and from said substrate;
- and
- means for setting the potential of said well region to be sufficiently more attractive to electrons than the potential of said overlying control gate so as to cause electrons to tunnel from said floating gate to said channel region, and for setting the potential of said well region to be less attractive so as to prevent electrons from tunneling from said floating gate to said channel region and allow electrons to tunnel from said channel region to said floating gate.
5 more elements
An electrically erasable and programmable transistor, comprising:
- a semiconductive substrate;
- a source and a drain defining a channel region therebetween in said substrate;
- an insulated floating gate at least partially overlying said channel region;
- a dielectric film between said floating gate and said substrate, said film having a thin tunneling region overlying said channel;
- a control gate overlying said floating gate and spanning said channel region, said control gate insulated from said floating gate and from said substrate;
- means for setting the potential of said overlying control gate to be sufficiently more attractive to electrons than the potential of said channel region to allow electrons to tunnel from said channel region to said floating gate;
- and
- means for lowering the potential of said source so that electrons flow from said source into said channel region and tunnel to said floating gate whenever said control gate is set at said attractive potential, and for setting the potential of said source to be sufficiently near the potential of said drain to stop electrons from flowing from said source into said channel and prevent electron tunneling to said floating gate.
5 more elements
An electrically erasable and programmable transistor, comprising:
- a semiconductive substrate of a first conductivity type;
- a well region in said substrate of a second conductivity type;
- a source and a drain of said first conductivity type inside said well region defining a channel region therebetween;
- an insulated floating gate at least partially overlying said channel region;
- a dielectric film between said floating gate and said substrate, said film having a thin tunneling region overlying said channel region;
- a control gate overlying said floating gate and spanning said channel region, said control gate insulated from said floating gate and from said substrate;
- means for setting the potential of said overlying control gate to be sufficiently more attractive to electrons than the potential of said well region to allow electrons to tunnel from said channel region to said floating gate;
- and
- means for lowering the potential of said source so that electrons flow from said source into said channel region and tunnel to said floating gate whenever said control gate is set at said attractive potential, and for setting the potential of said source to be sufficiently near the potential of said drain to stop electrons from flowing from said source into said channel and prevent electron tunneling to said floating gate.
6 more elements
An electrically erasable programmable read only memory formed on a first conductivity type semiconductive substrate, comprising:
- an opposite conductivity type well region in the top surface of said substrate;
- a plurality of first conductivity type source and drain strips in said well region arranged in source and drain pairs extending parallel to one another in transverse rows of said pairs;
- a plurality of control gate conductive strips overlying said substrate and insulated therefrom, said control gate strips extending parallel to one another in longitudinal columns overlying said transverse rows to define a plurality of source-to-drain channel regions underlying said control gate strips;
- a plurality of insulated floating gates overlying individual ones of said channel regions;
- an insulating film between said plurality of floating gates and said substrate, including a plurality of thin tunneling regions individually overlying said source-to-drain channel regions;
- and
- means for setting the potential of said well region to be sufficiently more attractive to electrons than the potential of at least one of said overlying control gate strips so as to cause electrons to tunnel from at least one of said floating gates to said substrate, and for setting the potential of said well region to be less attractive so as to prevent electrons from tunneling from said plurality of floating gates to said substrate and allow electrons to tunnel from at least one of said channel regions to a corresponding one of said floating gates.
4 more elements
An electrically erasable programmable read only memory formed on a first conductivity type semiconductive substrate, comprising:
- an opposite conductivity type well region in the top surface of said substrate;
- a plurality of first conductivity type source and drain strips in said well region arranged in source and drain pairs extending parallel to one another in transverse rows of said pairs;
- a plurality of control gate conductive strips overlying said substrate and insulated therefrom, said control gate strips extending parallel to one another in longitudinal columns overlying said transverse rows to define a plurality of source-to-drain channels underlying said control gate strips;
- a plurality of insulated floating gates overlying individual ones of said channels;
- an insulating film between said plurality of floating gates and said substrate, including a plurality of thin tunneling regions individually overlying said source-to-drain channels;
- means for setting the potential of a selected one of said overlying control gate strips to be sufficiently more attractive to electrons than the potential of said well region to allow electrons to tunnel from said well region to at least one of said floating gates;
- and
- means for lowering the potential of a selected one of said source strips so that electrons flow from said source strip beneath said selected control gate strip and tunnel into the corresponding one of said plurality of floating gates whenever said selected control gate strip is set at said attractive potential, and for setting the potential of unselected ones of said source strips to be sufficiently near the potentials of said plurality of drain strips to stop electrons from flowing from said unselected source strips beneath said plurality of control gate strips.
5 more elements
An electrically erasable programmable read only memory formed on a semiconductive substrate, comprising:
- a plurality of source and drain strips in said substrate arranged in source and drain pairs extending parallel to one another in transverse rows of said pairs;
- a plurality of control gate conductive strips overlying said substrate and insulated therefrom, said control gate strips extending parallel to one another in longitudinal columns overlying said transverse rows to define a plurality of source-to-drain channel regions underlying said control gate strips;
- a plurality of insulated floating gates overlying individual ones of said channel regions;
- an insulating film between said plurality of floating gates and said substrate, including a plurality of thin tunneling regions individually overlying said source-to-drain channel regions;
- and
- means for setting the potentials of said plurality of channel regions to be sufficiently more attractive to electrons than the potential of at least one of said overlying control gate strips so as to cause electrons to tunnel from at least one of said floating gates to said substrate, and for setting the potentials of said channel regions to be less attractive so as to prevent electrons from tunneling from said plurality of floating gates to said substrate and allow electrons to tunnel from at least one of said channel regions to a corresponding one of said floating gates.
3 more elements
An electrically erasable programmable read only memory formed on a semiconductive substrate, comprising:
- a plurality of source and drain strips in said substrate arranged in source and drain pairs extending parallel to one another in transverse rows of said pairs;
- a plurality of control gate conductive strips overlying said substrate and insulated therefrom, said control gate strips extending parallel to one another in longitudinal columns overlying said transverse rows to define a plurality of source-to-drain channel regions underlying said control gate strips;
- a plurality of insulated floating gates overlying individual ones of said channel regions;
- an insulating film between said plurality of floating gates and said substrate, including a plurality of thin tunneling regions individually overlying said source-to-drain channel regions;
- means for setting the potential of a selected one of said overlying control gate strips to be sufficiently more attractive to electrons than the potential of said substrate to allow electrons to tunnel from said substrate to at least one of said floating gates;
- and
- means for lowering the potential of a selected one of said source strips so that electrons flow from said source strip into the corresponding one channel region underlying said selected control gate strip and adjacent said selected source strip and tunnel into the corresponding floating gate whenever said selected control gate strip is set at said attractive potential.
4 more elements
An electrically bit-erasable programmable read only memory formed on a semiconductive substrate of a first conductivity type, comprising:
- a plurality of mutually isolated well regions of a second conductivity type in said substrate;
- a plurality of source and drain strips of said first conductivity type arranged in source and drain pairs extending parallel to one another in transverse rows of said pairs, each of said pairs individually residing in a corresponding one of said well regions;
- a plurality of control gate conductive strips overlying said substrate and insulated therefrom, said control gate strips extending parallel to one another in longitudinal columns overlying said transverse rows to define a plurality of source-to-drain channel regions underlying each of said control gate strips;
- a plurality of insulated floating gates, each of said floating gates overlying individual ones of said channel regions;
- an insulating film between of said floating gates and said substrate, including a plurality of thin tunneling regions individually overlying each of said channel regions;
- and
- means for applying a potential to selected ones of said well regions, said potential being sufficiently more attractive to electrons than the potential of the corresponding control gate strips, so as to cause electrons to tunnel from corresponding ones of said floating gates to said substrate, and for removing said attractive potential so as to prevent electron tunneling from said floating gates and allow electrons to tunnel from at least one of said channel region to said floating gate.
4 more elements
Dependencies are inferred from the claim text.