Digital input apparatus
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorYukio Urushibata
Life of this patent
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Abstract
A digital input apparatus is provided which is used as an input apparatus for a digital signal processor and can eliminate noise components resulting from electromagnetic induction and resulting from chattering which is produced by the opening or closing of a contact. One input signal outputted from the multiplexer (105) is applied through a latch flip-flop (108) to a counter (114) used on a time sharing basis so that counting is effected. Individual counts corresponding to a plurality of input signals are stored in a memory (117). When a count becomes all "1's" or "0's", the counter (114) produces a carry signal or a borrow signal supplied to a J-K flip-flop (113). The J-K flip-flop (113) produces an input signal of a predetermined waveform free from noise components.
Claims11
A digital input apparatus comprising
- multiplexer means adapted to receive a plurality of input signals and select a desired input signal for outputting;
- first latch means connected to said multiplexer means to latch the output signal selected by said multiplexer means;
- counter means for effecting a count operation from an output signal from said first latch means;
- second latch means connected to said counter means to latch an output signal from said counter means;
- gate means connected between the first latch means and said counter means to control a signal inputted to said counter means by the output of said counter means;
- memory means connected to said counter means and to an output signal from said second latch means for storing a count of said counter means and the output signal from said second latch means;
- and
- timing signal generating means for supplying timing signals to the multiplexer means, said counter means and said memory means and for supplying an address control signal to said multiplexer means and said memory means.
Dependencies are inferred from the claim text.