Fast charge transfer analog-to-digital converter

A pipelined analog-to-digital converter for generating by successive approximation a digital word having a plurality of binary bits defining the magnitude of a pipeline input source signal, comprising:

• a plurality of stage means serially connected to form a pipeline register for serially passing at least one source signal, each stage means generating a binary bit for a particular bit position of said digital word and each stage means having,
• at least one storage means for receiving and storing at least a source signal;
• reference generating means for generating a reference signal,
• splitting means for dividing the reference signal into a comparator signal component and a modification signal component, the magnitude of the comparator signal and the modification signal defined in accordance with the bit position of the binary bit of the stage means within said digital word,
• comparator means for comparing the stored source signal with the comparator signal and for generating a binary bit in accordance with the result of the comparison,
• means for passing the stored source signal to a next successive stage means after the comparator means has compared the source signal and the comparator signal, and
• transfer means responsive to the generation of a particular binary bit by said comparator means for passing the modification signal to the next successive stage means to combine the modification signal with the source signal of the next successive stage means.

A pipelined CCD charge splitter for receiving input reference charge packets Q.sub.R and dividing each of the received packets into a plurality of fractional charge packets, the charge splitter comprising:

• a first charge splitting electrode and means for energizing the electrode to form two potential wells of equal charge capacity, each potential well receiving one half of the Q.sub.R input charge packet to form two Q.sub.R /2 charge packets;
• a first buffer electrode arranged in insulated, overlapping relation to the first charge splitting electrode and means for energizing the first buffer electrode to form a summing potential well and a storage potential well and for de-energizing said first charge splitting electrode to move one Q.sub.R /2 charge packet of the first charge splitting electrode into the summing potential well and the other Q.sub.R /2 charge packet into the storage potential well;
• successive alternating charge splitting and buffer electrodes arranged in insulated, overlapping relation, the first electrode of the successive electrodes being a charge splitting electrode arranged in insulated, overlapping relation with said first buffer electrode, each successive charge splitting electrode responsive to an energization signal for forming two potential wells of equal charge capacity and an additional potential well and each successive buffer electrode responsive to an energization signal for forming a summing potential well and a storage potential well;
• means for energizing each successive charge splitting electrode and de-energizing the associated preceding buffer electrode so that the two equal charge capacity potential wells of the energized charge splitting electrode receive equal portions of the charge of the storage well of the preceding buffer electrode and the additional potential well of the energized charge splitting electrode receives the charge of the summing well of the preceding buffer electrode;
• and
• means for energizing each successive buffer electrode and de-energizing the associated preceding charge splitting electrode so that the summing potential well of the energized buffer electrode receives charge from the additional potential well and one of the equal charge capacity potential wells of the preceding charge splitting electrode and the storage potential well of the energized buffer electrode receives the charge from the other of the equal charge capacity potential wells of the preceding charge splitting electrode.