Back to results
US 4,375,037 AGranted
Receiving circuit
AssigneeHitachi, Ltd.
InventorIchiro Ikushima
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeHitachi, Ltd.
InventorIchiro Ikushima
Estimating the term…
In a receiving circuit wherein a digital input signal is compared with a reference voltage and is regenerated into a pulse information signal of "1" or "0" value, a circuit for producing the reference voltage is constructed of a peak detector circuit which detects the maximum value of the output of a preprocessing circuit for the input signal, a reference preprocessing circuit which has the same circuit arrangement as that of the first-mentioned preprocessing circuit except for receiving no input signal, and a voltage divider circuit which divides the sum of the output of the peak detector circuit and an output of the reference preprocessing circuit. With such an arrangement, even when the amplitude of the input digital signal has fluctuated, a pulse signal whose pulse width is subjected to substantially no variation can be regenerated by means of the simple circuitry.
A receiving circuit for detecting and regenerating a pulse signal, comprising a preprocessing circuit having a predetermined circuit composition which receives digital signals having low and high amplitude valves as input signals, a reference voltage circuit which produces a reference voltage on the basis of the output signal of said preprocessing circuit, and a comparator circuit which compares the output signal of said preprocessing circuit with said reference voltage for regenerating said digital signals, said reference voltage circuit comprising a peak detector circuit connected to the output of said preprocessing circuit for detecting the maximum value of the output of said preprocessing circuit, means including a reference preprocessing circuit which has the same circuit composition as that of said first-mentioned preprocessing circuit and to which no input signal is applied for producing an output voltage having a predetermined relationship to said low amplitude value of said input signals, and a voltage divider circuit which divides the sum of the output voltage of said peak detector circuit and the output voltage of said reference preprocessing circuit, the divided output of said voltage divider circuit being applied as said reference voltage to said comparator circuit along with the output of said first-mentioned preprocessing circuit.
Dependencies are inferred from the claim text.