Clock failure monitor circuit employing counter pair to indicate clock failure within two pulses

A pulse monitor circuit for use in a switching system, said pulse monitor comprising:

• a first source of periodic pulses;
• a second source of periodic pulses;
• input storage means connected to said first pulse source, operated in response to each of a first group of alternately occurring pulses from said first pulse source to generate a first clear signal, said input storage means further operated in response to each of a second group of alternately occurring pulses from said first pulse source to generate a second clear signal;
• a first counter circuit connected to said input storage means and said second pulse source, operated in response to an absence of said first clear signal to count pulses from said second pulse source;
• a second counter circuit connected to said input storage means and said second pulse source, operated in response to an absence of said second clear signal to count pulses from said second pulse source;
• and
• output storage means connected to said first and second counter circuits, operated in response to a predetermined count from said first or second counter circuits to generate a pulse failure signal.