Charge-pumping MOS FET memory device

A semiconductor memory device comprising:

• an electrically floating semiconductor layer;
• a source and a drain region formed in said semiconductor layer;
• a gate insulating layer formed on said semiconductor layer and a gate electrode formed on said insulating layer;
• said memory device having a threshold voltage for conduction of a first value and normally storing one of "0" and "1" information values;
• means for selectively applying a gate voltage to said gate electrode exceeding said first threshold voltage value of said device to produce a bias voltage in said semiconductor layer, said semiconductor layer storing said bias voltage produced by said gate voltage and establishing thereby a threshold voltage of a second value different from said first value, thereby to store the other of said "0" and "1" information values;
• said memory device selectively storing "0" and "1" information values in accordance with a desired, predetermined relationship of said "0" and "1" information values and said different bias and corresponding threshold voltage values;
• said semiconductor layer further comprising a central region having a low threshold voltage and side regions having a high threshold voltage, formed in said semiconductor layer between said source region and said drain region;
• said first voltage threshold value being determined by said high threshold voltage of said side regions, and said side regions undergoing pinch-off prior to pinch-off occurring in said central region upon removal of said selectively applied gate voltage and
• means for producing a read-out current from said memory device, the level of the read-out current differing in accordance with the different bias and corresponding threshold voltage values and thereby affording read-out of the information value stored in said memory device.