US 4,371,932 AGranted

I/O Controller for transferring data between a host processor and multiple I/O units

AssigneeInternational Business Machines Corporation

InventorsJohn M. Dinwiddie, Jr., Bobby J. Freeman, Timothy Jackson, William L. Zipoy

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Abstract

An I/O controller for transferring data between a host processor and one or more I/O devices. This I/O controller includes a microprocessor, a direct memory access controller and a dual port storage unit, one port of which is coupled to the host processor I/O channel bus and the other port of which is coupled to the microprocessor bus. All data transfers are by way of the dual port storage unit. The I/O controller includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between the host processor and the I/O controller. In particular, this interleaving mechanism enables host processor direct program control (DPC) data transfers to be performed at the same time that the I/O controller is busy doing cycle steal data transfers for a block of data. These DPC data transfers are accomplished without interrupting the cycle stealing operations.

Claims12

Dependent claims

An I/O controller for transferring data between an I/O unit and a host processor having a main storage unit and comprising:

a random access controller storage unit located in the I/O controller for storing data;
first selectively operable data transfer circuitry for providing a data transfer path between the host processor and the controller storage unit;
second selectively operable data transfer circuitry for providing a data transfer path between the controller storage unit and the I/O unit;
first storage accessing circuitry for supplying addresses to the controller storage unit and selection signals to the second data transfer circuitry for enabling the transfer of data between the controller storage unit and the I/O unit;
cycle steal storage accessing circuitry for supplying host processor main storage addresses to the host processor, controller storage addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data words between the host processor and the controller storage unit in a cycle steal data transfer mode wherein a plurality of data words are automatically transferred by the I/O controller without need for individual word I/O commands from the host processor;
direct command storage accessing circuitry responsive to addresses received from the host processor for supplying addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data words between the host processor and the controller storage unit in a direct command data transfer mode wherein one data word is transferred for each I/O command issued by the host processor;
and interleaving control circuitry coupled to the second and third storage accessing circuitry for enabling the transfer of a data word to be transferred in the direct command data transfer mode to be interleaved between the transfer of two data words being transferred in the cycle steal data transfer mode.

4 more elements

An I/O controller adapted to be coupled to the I/O channel bus of a host processor and to an I/O unit for transferring data between the host processor and the I/O unit and comprising:

a microprocessor for supervising data transfer activities;
a microprocessor bus coupled to the microprocessor and adapted to be coupled to the I/O unit;
a random access storage mechanism for storing data and including address circuitry for addressing the different storage locations in such mechanism;
address responsive circuitry responsive to the occurrence of predetermined address bits on the host processor channel bus for producing an allow host connect signal;
address selector circuitry having a first set of inputs coupled to the microprocessor bus and a second set of inputs coupled to the host processor channel bus for selectively transferring address bits from either the microprocessor bus or the host processor channel bus to the address circuitry of the random access storage mechanism and responsive to the occurrence of the allow host connect signal for selecting the host processor address bits for such transfer;
first selectively operable data transfer circuitry having a first set of signal transfer terminals coupled to the host processor channel bus and a second set of signal transfer terminals coupled to the data terminals of the random access storage mechanism and being responsive to the occurrence of the allow host connect signal for providing a data transfer path directly between the host processor channel bus and the random access storage mechanism;
and second selectively operable data transfer circuitry having a first set of signal transfer terminals coupled to the data terminals of the random access storage mechanism and a second set of signal transfer terminals coupled to the microprocessor bus and operative during the absence of the allow host connect signal for providing a data transfer path directly between the random access storage mechanism and the microprocessor bus.

4 more elements

Dependencies are inferred from the claim text.