US 4,371,929 AGranted

Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory

AssigneeIBM Corporation

InventorsJohn J. Brann, Charles S. Freer, Jr., Warren W. Jensen

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Abstract

In a multiprocessor system, a controllable cache store interface to a shared disk memory employs a plurality of storage partitions whose access is interleaved in a time domain multiplexed manner on a common bus with the shared disk to enable high speed sharing of the disk storage by all of the processors. The communication between each processor and its corresponding cache memory partition can be overlapped with each other and with accesses between the cache memory and the commonly shared disk memory. The addressable cache memory feature overcomes the latency delay which inherently occurs in seeking the beginning of a region to be accessed on the disk drive mass storage.

Claims12

Dependent claims

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising:

a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk drive memory, for storing data sets for each of said processors in mutually exclusive partitions;
a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory;
word counter in said DMA controller having an input connected to a selected processor, for counting the quantity of data stored in the corresponding partition of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partition to said disk drive memory;
whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

1 more element

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising:

a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus;
a disk adapter connected between said disk drive memory and said common data bus;
a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions;
a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory;
a word counter in said DMA controller having an input connected to a selected host adapter, for counting the quantity of data stored in the corresponding partition of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partition to said disk drive memory;
whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

3 more elements

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising:

a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk memory, for storing data sets for each of said processors in mutually exclusive partitions;
a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory;
a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said processors, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory;
said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors;
a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory;
said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory;
whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

4 more elements

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising:

a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus;
a disk adapter connected between said disk drive memory and said common data bus;
a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions;
a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory;
a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said host adapters, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory;
said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors;
a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory;
said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said host adapters or said disk adapter;
whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

6 more elements

Dependencies are inferred from the claim text.