Semiconductor differential amplifier circuit with feedback bias control
AssigneeBell Telephone Laboratories, Incorporated
InventorsSan-Chin Fang, Donald L. Fraser, Jr.
Life of this patent
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Abstract
An input differential amplifier stage (10), which feeds an output stage (20), has a feedback loop originating at a node (N.sub.1) in one branch, for controlling the current-source transistor (M.sub.5) of that stage. The feedback loop is characterized by a direct connection to the gate electrode of a transistor (M.sub.8) which drives the output stage (20), while the output at another node (N.sub.2), in the other branch of the differential amplifier stage (10) is fed to another transistor (M.sub.9) which also drives the output stage (20).
Claims13
Semiconductor apparatus in MOS technology comprising a differential amplifier input stage (10) including a pair of substantially identical first and second mutually parallel branches (M.sub.1 M.sub.3 and M.sub.2 M.sub.4) having, respectively, first and second output nodes (N.sub.1, N.sub.2), said branches being connected through a common third node (N.sub.3) to a controlled terminal of a common current-source transistor (M.sub.5) for supplying current to both said branches, CHARACTERIZED IN THAT the first output node (N.sub.1) of the first branch is directly connected to the gate electrode of a first auxiliary transistor (M.sub.6) having one of its controlled terminals connected to a feedback node (N.sub.F) which is connected both to the gate electrode of a first intermediate amplifier transistor (M.sub.8) and to the gate electrode of said current-source transistor (M.sub.5).
A differential amplifier stage (10) which comprises:
- (a) a first input MOS transistor (M.sub.1) whose source-drain path is connected in series with that of a third MOS transistor (M.sub.3), thereby forming a first node (N.sub.1) between their respective source-drain paths;
- (b) a second input MOS transistor (M.sub.2) whose source-drain path is connected in series with that of a fourth MOS transistor (M.sub.4), thereby forming a second node (N.sub.2) between their respective source-drain paths;
- (c) a current-source MOS transistor (M.sub.5) whose source-drain path is connected to a third node (N.sub.3) to which the source-drain paths of the first and second transistors (M.sub.1, M.sub.2) are connected in common;
- (d) a feedback loop from said first node (N.sub.1) to a feedback node (N.sub.F) connected to the gate electrode of the current-source transistor (M.sub.5), said feedback loop including a first auxiliary transistor (M.sub.6) having one of its controlled terminals connected to the feedback node (N.sub.F) and having its gate electrode directly connected to the first node (N.sub.1);
- (e) a first intermediate amplifier MOS transistor (M.sub.8) whose gate electrode is connected to the feedback node (N.sub.F).
Dependencies are inferred from the claim text.