Automatic fault recovery system for a multiple processor telecommunications switching control

In a call switching system control complex, which includes multiple processors each having a processing unit and a memory unit, with at least one of said memory units having an active and a standby copy thereof, a fault recovery system comprising:

• means, responsive to the processing unit in one of said processors reading data from a selected location in the active copy of an associated memory unit, for generating a return data parity error indication when the data read contains a parity error;
• means for reading standby data from a location, in the standby copy of the associated memory unit, corresponding to said selected location in the active copy and writing the standby data into said selected active copy location;
• and
• means upon a subsequent return data parity error indication in said one processor for switching the standby copy of the memory unit thereof, as available, to active status and the active copy thereof to standby status.

In a call switching system control complex, which includes a processor having a processing unit and a memory unit, with said memory unit having an active and a standby copy thereof, each with stored contents, a fault recovery system assuring that said standby copy is in condition to become active when required, comprising:

• means, operational in the presence of ongoing call switching by said system, upon determination that call switching activities are presently not required of the processor, for initiating reading and storing a multiple byte portion of the contents of said standby copy;
• means for comparing said portion read and stored with the contents of the comparable portion of said active copy;
• and
• means, in the event said portions do not compare, for correcting the standby copy by writing contents of the active copy to the standby copy.

In a call switching system control complex which includes multiple processors each having a processing unit and a memory unit with data written therein, with at least two of said units, including one of said processing units having active and standby copies thereof, a fault recovery system comprising:

• means for responding to an indication of an error in one of said processors by rewriting a portion of the memory unit of said one processor;
• means for recording the occurrence of said indication of an error and, upon a subsequent indication of an error in said one processor, for switching a standby copy therein, as available, to active status and the corresponding active copy to standby status;
• and
• means, upon a different indication of an error in said one processor, for rewriting a portion of each of the memory units of all said processors.

In a call switching system control complex which includes multiple processors each having a processing unit and a memory unit, with at least one of said memory units having an active and a standby copy thereof, a fault recovery system comprising:

• means for generating a return data parity error indication when one of said processing units reads data containing a parity error from a selected location in the active copy of an associated memory unit;
• means for designating a fault giving rise to the error indication as being hard or soft, including
• means for reading standby data from a location, in the standby copy of the associated memory unit, corresponding to said selected location in the active copy and writing the standby data into said selected location of said active copy,
• means for rereading from said selected location in said active copy, and
• means for classifying said fault as hard upon the occurrence of a return data parity error indication accompanying said rereading, and for classifying said fault as soft in the absence of said occurrence.

In a call switching system control complex, which includes multiple processors each having a processing unit and a memory unit, with at least one of said memory units having an active and a standby copy thereof and at least one of said processing units having an active and a standby copy thereof, a fault recovery system comprising:

• means for generating a return data parity error indication in one of said processors, when the processing unit thereof reads data containing a parity error from a selected location in the active copy of an associated memory unit;
• means for designating a fault giving rise to the error indication as being hard or soft, including means for reading standby data from a location, in the standby copy of the associated memory unit, corresponding to said selected location in the active copy and writing the standby data into said selected active copy location;
• means, upon the designation of said fault as hard in said one processor memory unit, for switching the standby copy thereof to active status and the active copy thereof to standby status;
• means, upon the designation of said fault as soft, for keeping a count of the occurrences of said indication of an error associated with a soft fault;
• and
• means, upon reaching a selectable count of said error indications associated with a soft fault in said one processor, for switching the standby copy of the memory unit thereof, as available, to active status and the active copy thereof to standby status.

In a call switching system control complex, which includes multiple processors each having a processing unit and a memory unit, with at least one of said processors having processing unit copies classified according to operational status as active and standby copies, a fault recovery system comprising:

• hardware watchdog timer means, associated with one processor having said copies, for generating an overflow indication whenever the timer means is not reset by the action of said one processor within a predetermined interval;
• means for keeping a count of occurrences of said overflow indications;
• means upon occurrence of one of said overflow indications and when the count of such indications is less than a first preselected number, for initializing a portion of the memory unit of said one processor;
• and
• means, upon the count of said overflow indications becoming equal to said preselected number, for switching the standby copy of the processing unit of said one processor to active status and the active copy thereof to standby status.

In a call switching system control complex, a fault recovery system comprising:

• a processing unit;
• first and second bus multiplexers, each in communication with said processing unit, and each of said bus multiplexers having associated exclusively therewith one or more memory units, each switchable to active or standby status, thereby providing for one memory unit associated with one of the multiplexers to be an active copy, corresponding to a standby copy memory unit associated with the other multiplexer;
• bus configuration means under the control of said processing unit for permitting said processing unit to write to both said bus multiplexers in a duplex mode or to a selected one of said multiplexers in a simplex mode;
• means for generating an indication of an error related to said memory units;
• means for responding to said indication of an error by writing from the standby copy, of a particular memory unit associated with one of said bus multiplexers, to the active copy thereof, by
• commanding simplex operation between the processing unit and the bus multiplexer associated with the particular memory unit standby copy,
• commanding the particular memory unit standby copy to active status,
• reading from the memory unit copy with changed status,
• restoring the memory unit copy read from to standby status,
• commanding duplex operation between the processing unit and the bus multiplexers, and
• writing to both copies of the particular memory unit;
• and
• means, upon a subsequent indication of an error, for switching a standby copy of said memory units to active status and the corresponding active copy to standby status.